Hardware Design Engineer Resume Sunnyvale, CA - Hire IT People

OBJECTIVE:

Seeking a full - time position in analog/mixed signal or RF design; open to relocation.

PROFESSIONAL EXPERIENCE:

Confidential

Hardware Design Engineer

Responsibilities:

Bring new concepts into reality in the server business by working with hardware engineers and HP Laboratory staff. Currently testing out modules for next generation enterprise server.
Identified DRAM type to be used for next generation enterprise server; co-designed prototype for future dual inline memory module (DIMM).
Characterized millimeter-wave Schottky barrier diode voltage detector (Bulk CMOS 45-nm; up to 110GHz).
Designed/tape-out millimeter-wave phase detector. (Bulk CMOS 45-nm.)
Designed/tape-out/characterized 77GHz amplifier; characterized 60GHz tunable amplifier. (Bulk CMOS 45-nm.)
Instrument: PNA/PXA/E8257D PSG/ELVA Power Meter/E4407B spectrum analyzer and more.

Confidential -Sunnyvale, CA

Customer Applications Engineer

Responsibilities:

Co-generate datasheets with product definer and designers before product introduction (RF transmitter/receiver, analog switches, high voltage protector, and temperature sensors).
Independent IC specification verification through measurement and provide design changes.
Providing telephone/email technical support for wireless ICs and non-wireless ICs of Confidential (except ASIC, Fiber, and Confidential -Dallas parts).

Confidential - Santa Clara, CA

Electrical Engineer

Responsibilities:

Designed a power entry board that does power distribution circuitry, relay logic, and over current protection.
Optimizing board level layout and functionally verifying/validating the class-E amplifier (13.6 MHz) board and power entry board; integration of all modules of the abatement system including testing/troubleshooting.
FPGA programming (both schematic & verilog) for PDM/PWM for driving the amplifier for power manual adjustment.
Input design transfer effort, ensuring product reliability and future scalability.
Participate design/development direction decision making.

Confidential

Electrical Engineer Intern

Responsibilities:

Layout for varactors, MOM/MIM with 0.13um, 90nm, and 65nm design rules using Cadence Virtuoso’s SKILL.
Measurement characterization of MOS and capacitors in RF (up to 67GHz)/DC.
Instrument: Cascade S-300 plus Agilent 8510C VNA, 4156A (precision semiconductor parameter analyzer), 4284A (LCR precision meter) for RF (up to 67GHz)/DC characteristics of varactors and MIMs.

Confidential

Electrical Engineer Intern

Responsibilities: