OBJECTIVE: A Sr. Test Engineer position.

SUMMARY OF QUALIFICATIONS:

Hardware:

• Hardware Implementation Languages: VHDL, Verilog HDL, AHDL, ABEL.
• Hardware design simulation tools: Cadence Leapfrog, Synopsys Design Analyzer, Synplicity FPGA Expresstool,Altera, Xilinx, Viewlogic, Lattice ISP, and Microsim Spice simulation tool; also familiar with Oscilloscope, Logic Analyzer, Logic Probe, and Emulators.

Operating Systems:

• Familiar with Unix/Linux/Windows/DOS.

Software Languages:

• TCL/TK, Perl, C, C++ Programming.

Networking Knowledge:

• Familiarize Cisco Internetwork Operating System (IOS) fundamentals, OSI Model and Layer Communication, Bridge/Switches and LAN design, Network protocols, RIP, IGRP routing, Access List Security and WAN protocols.
• Attended the Cisco Voice over IP, ATM, Frame Relay and Interconnecting Cisco Network Devices.

WORK HISTORY:

04/10- Present
Confidential
San Jose, CA
Sr. Test Engineer.

• Working in ESTG Escalation team interfacing with Engineering and CA to improve the quality and customer satisfaction of ESTG products by working on software and hardware defects,
• Driving quality back into the Engineering organization
• Develop on EDVT to find the root causes and mitigate the risks.
• Write test plans for EDVT testing to duplicate the failures in fields.
• Debugging on hardware and software to root cause the issues.

10/07-01/10
Confidential
San Jose, CA
Sr. Optical Test Engineer.

• Working on StrataLight 40Gbps DWDM transport line card with modulation scheme such as Atlas, Redstone on 260, 700 and 800 level. StrataLight\'s 40 Gbps transponder technology supports long-haul transmission using EDFA-only or ultra long-haul using Raman-assisted amplification.
• Interfacing with manufacturing process, hardware engineers at SLC.
• Debugging or troubleshooting on board level and system level on Atlas and Redstone on 260 and 700-level to find the root-cause and feedback the issues back to process, manufacturing and component engineers to take immediately corrective actions on Sanmina and customer site.
• Collecting and analyzing test yield data by Pareto Diagrams in Excel.
• Developing test plans for New Production Instruction ( NPI ) for several products simultaneously and under very challenging timeliness.
• Reviewing customer-provided documentation for completeness and consistency and generating required test documentation.
• Working with engineers at SLC to set up test stations 260, 700 and 800 level on Sanmina site.
• Calibrating StrataLight OTS-4000 DPSK Line Card 700 Level Test Bed.
• Giving training to Jr. Test Engineer and test technicians.

04/2000-09/2007
Confidential
San Jose, CA
Sr. Test Engineer.

• Qualify and verify Marvell and Broadcom Gigabit Ethernet Transceivers on Cisco 2K and 3K Switch products complied with IEEE standard using Scopes, Probes, Power Modules, Analyzers, Jitter measurement tools, Generators-Pulse, Function, Traffic Generators, Hypot and CDE, Test Jigs 10/100/1000 IEEE
• Develop on Fault Insertion in order to find bugs on hardware, diagnostics, and IOS.
• Develop on EDVT to find the root causes and mitigate the risks.
• Write test plans
• Bring up and test prototype boards
• Debug and troubleshoot the failed boards as necessary
• Provide weekly status to the team
• Integrated the systems as needed.
• Distribute boards or systems to the team projects per schedule.
• Train the other Test Engineer as needed

1998 - 2000
Confidential
Milpitas, CA
Sr. Test Engineer.

• Diagnose PCB failures to components level using 16500B Logic Analyzer, 1Ghz TDS Digitizing Oscilloscope, DMM, etc.
• Ensure adherence to corporate quality standards and customer quality requirements. Collect, analyze, monitor quality data and report, delineating between components and process issues.
• Support Production and execute the OEM of ISO 9002.
• Work on Project such as DELL COMPUTER and EXTREME NETWORKING.
• Implement and maintain troubleshooting equipment and test and diagnostic software programs.
• Design test fixtures as needed and program test equipment and/or develop test strategies and process for products being introduced to production.
• Develop Test Process Instruction documentations to establish test requirements and processes.
• Interface with other engineering functions, and possibly customers, to resolve test yield and test time issues as required, make recommendation to improve processes for testability.
• Interface with functional owners on quality (CFT) and with customers on customer-related issues.

1996-1998
Confidential
Sunnyvale, CA
Test Engineer.

• Develop the test program on Caesar tester to characterize DC, AC, and Logical functional on PCI9060, PCI9080 bus interface chips.
• Verify design specifications by using Cadence and Synopsis tools.
• Use 16500B Logic Analyzer and 500Mhz TDS Digitizing Oscilloscopes to verify Errata
• Generate Waveforms for Blue Book by conversion of VCD files to Timing Diagram.
• Be familiar with Intel 80960 Family, MPC860, Power PC40x Family, Power PC60x Family and familiar with PCI Local Bus Specification Revision 2.1 & 2.2.

1992-1995
Confidential
Saint Petersburg, FL
Test Engineer.

• Develop the test programs for improving efficiency and throughput of the diagnosis of assemblies on board level. Diagnose and troubleshoot to the component level for assemblies not passing required functional test.
• Support production engineers to resolve any PCB test yield problems, including finding root causes of problems and monitoring the improvements. The projects working on such as Motherboard of Super Micro, Motherboard, PCI Dual SCSI Adapter, PCI NVRAM of NetWork Appliance, PCI Video Card of TrueVision,
  Synchronous Burst Cache Module of ISSI.
• Utilize DMM, 500Mhz TDS Digitizing Oscilloscopes, Power Supplies, Function Generators, 16500B Logic Analyzers to diagnose and debug. Maintain test procedures, test fixture and software on HP3070 Series II.
• Interface with customers’ design engineers. Train technicians.

EDUCATION:

• Master of Science in Electrical Engineering.
• Bachelor of Science in Electrical Engineering.