Quality Control Engineer Resume Santa Clara, CA - Hire IT People

Objective – To obtain challenging position as an Electrical Engineer to contribute knowledge of Analog and Mixed Signal Integrated Circuits to deliver high quality commitment with self-motivation and dedication

Work Experience

Analog IC Design Intern at Confidential, Santa Clara, CA Sept 11 - July 12

Design, test and debug of embedded analog and mixed signal circuits, such as high speed I/O, SerDes, VCO, PLL, CDR.
Perform corner PVT test, MIPI D-PHY compliance test, Jitter tolerance, Skew optimization, DCD measurement using the lab equipment like oscilloscope.
Characterization and debugging of chip, Prepare test reports, Perform simulation using spice circuit simulator.

Quality Control Engineer at Confidential Apr 09 - Jul 09

Perform electrical tests as per IS-7098 and IEC-60502 of cable.
Work as troubleshooter, Apply engineering judgments and make technical decision to solve the faults at site.
Communicate with clients and management throughout testing.

Technical Skills

Software: Cadence Design Suite (90nm, 0.13um, 0.25um) , Spice, Synopsys HSIM, Verilog, C Programming, MATLAB

Design Ability: Ring and LC Oscillator, Charge pump, PLL, DLL, VCO, Clock and Data Recovery, Fractional N-Synthesizer, Divider, Loop Filter, Band-gap Reference Circuit, Low Noise Amplifier, Broadband Amplifier, High Speed custom CMOS, LVDS, CML Logic, RX and TX drivers, FIR and DFE Equilizer, MUX, DeMUX, Current Mirrors, High Speed Channel, RFIC Design

Operating System: Linux/Unix, Mac, Windows

Application: Microsoft Office (word, excel, power point), Open Office 3.2

Completed certified course in programmable logic controller (Allen Bradley)

Projects

Phase Locked Loop Design. (Technology: TSMC 0.25um)

Design divide by 32 PLL with supply voltage 2.5V, output frequency 1.28 GHz, phase noise less than -90dbC/Hz and lock time of 1.5us.

Two Stage High Gain Op-Amp Design. (Technology: TSMC 0.25um)

A differential input and single-ended output Op-Amp with 1500 differential mode gain, 0.1 common mode gain, 1.4V output swing and maximum BW.

1:2 DeSerilizer Design (Technology: TSMC 0.13um)

Design 1:2 DeMux with 10Gbps data rate and, output swing 0.4V.

Limiting Amplifier for SONET Receivers. (Technology: TSMC 0. 13um)

Design Limiting Amplifier with 3 GHz BW and 32dB gain for SONET OC-48 application

Gigabit 16 x16 Crossbar Switch Design. (Technology: TSMC 0.25um)

Crossbars switch with 1 Gbps Data rate, 1 ns Latency, 50% duty cycle and, 16 input-output ports. Also design Physical layout with minimum area using cadence simulator and verify DRC, LVS.

Low Noise Amplifier Design (Technology: TSMC 0.13um)

Design LNA with 1.3V, 5.25GHz, 1.2dB NF, Maximum IIP3 and Minimum Power Dissipation

Education
M.S. in Electrical Engineering
Confidential University
Bachelor of Electrical Engineering
Confidential University

Relevant Courses
Semiconductor Devices and Circuits, Transistor Integrated Circuits, VLSI Design and Lab, CMOS RFIC Design, High Speed Communication Circuits, Data Communication, Digital Signal Processing, Digital Control System

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Quality Control Engineer Resume

Santa Clara, CA

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