SUMMARY

• Solid industrial experience on designing ASIC/FPGA IP and products. Expert knowledge on complete chip design cycle and steps from defining the macro architecture specification, to design, simulation, synthesis, implementation and verification.
• Capable of managing/coordinating a team. Strong communication skills. Team player. Adaptability in assuming multiple roles during a chip design cycle.
• Focusing on result with integrity and professionalism. Striving to achieve the highest standard of excellence.

PROFESSIONAL EXPERIENCE

Confidential, Santa Clara, California

Senior FPGA Design & Validation Engineer

Responsibilities

• Built Altera Stratix IV based Memory Controller validation platform. Synthesis using Synplify Premier. Place & Route using Altera Quartus. Run ASIC / FPGA simulation using MAKE, Tcl script. Debugged RTL using Verdi. Debugged firmware in C.
• Built FPGA Validation Platform for MPS2 project based on the HAPS - 54 board. Defined FPGA architecture, the interface between MPS2 ASIC chip, Virtex-5 FPGA and the test board. Created FPGA Linux/UNIX simulation environment in VCS/ModelSim and built test benches in System Verilog.

Confidential, Chandler, Arizon

Senior Design Verification Engineer

Responsibilities

• Applied RTL and system C coding to create the test bench to run object oriented programming ( OOP ) SystemVerilog simulations for the HDTV System on Chip ( SOC ) chip. Worked with architecture and design team to develop simulation and verification environments to prove the correctness and to measure performance of the algorithm and RTL.
• Worked on video interface such as Vby1, HDMI TX/RX, Component/VGA Video, composite video, Audio ADC, Audio DAC and display port. Created testplan, executed and achieved coverage targets. Created test benches in SystemVerilog to run simulations. Applied System - C and coverage driven random verification environment Open Verification Methodology ( OVM ) platform for validation testing.

Confidential, Santa Clara, California

Senior Staff Engineer

Responsibilities

• Led an engineering team of three members. Coached junior engineers.
• Prototyped ASIC chips Baldur and Luigi2 in Virtex - 5, and conducted functionality test through UART, XDB and RealView. These chips won significant market share in SATA/SAS storage market.
• Brought up and validated DDR2 memory controller and PCI Express slave in Virtex-5 on HAPS-34 development board using Synplify Pro, ISE, ChipScope, FPGA Editor, PlanAhead, Logic Analyzer, Oscilloscope, and Protocol Analyzer.
• Verified WiMedia Wireless USB System on Chip (SOC) using Synopsys Ultra Wide Band (UWB) IP in object oriented programming (OOP) Vera. Partitioned ASIC into two FPGAs. Conducted lab test for MOBA interface. Developped simulation environments used by test development team to exercise Matlab and Verilog models, as well as evaluate third party tools and develop methodologies which enhance ability to produce high quality ASICs.

Confidential San Jose, California

Senior ASIC Design & Verification Engineer

Responsibilities

• Designed PCI Express Bridge chips in Verilog/System Verilog, interfaced with system architects, wrote detailed design specification, defined clock/reset/power concept, integrated external IPs and conducted ECO s for netlist. PCI Express Bridge chips generated $8M annual revenue.
• Trained Application Engineers and Marketing team on technical knowledge.
• Generated test benches according to verification plan, set up regression test suite, and ran regression for RTL and Gate level simulation. Defined static timing constraints, ran synthesis tcl script for Synopsys Design Compiler and Timing Analysis script for PrimeTime.
• Designed modulator IC for a cable modem following DOCSIS CCCM specifications. Owned responsibility for three modules: Nyquist filter, Interpolator, and Upconverter.
• Simulated and verified the front end and backend of the modulator at RTL level including MAC interface, clock generator, FEC scrambler, differential encoder, symbol generator, and microprocessor interface. Conducted block level verification and system level verification by writing Verilog test benches, Perl, C and object oriented programming (OOP) C++ programs. Synthesized the modulator using AMBIT synthesis tool. Conducted gate level simulation.

Confidential, Fremont, California

Project Lead & Senior FPGA Design Engineer

Responsibilities

• Led Project Real Time Watermark Embedder. Managed 6 people team. Brought up 300% increase in revenue.
• Designed and simulated Real Time Watermark Embedder in Virtex - 4 on Xilinx Development Board ML403 using Xilinx Platform Studio (XPS), ModelSim and ISE in System Verilog. Defined product micro architectures. Lab tested VBI Closed Caption Detection and Insertion board with Virtex-II Pro. Performed HW/SW feature integration and functional verification.
• Designed Physical Layer Router (PLR) in VHDL by using Quartus enabling PLR to meet high speed timing requirement for DSL systems.
• Designed Tone Detector using Matlab, Simulink, DSPBuilder and Quartus. Applied newest approach for implementing DSP cores in FPGA.

Confidential, San Jose

ASIC Design Engineer

Responsibilities

• Wrote programs in VHDL for T1, E1, DS3, SONET handheld test and measurement equipment.
• Implemented Lockheed Martin Missiles & Space project VXI SERIAL IO Board testing with programmable data formatting using Xilinx Spartan Device.
• Designed Intellectual Property in imaging, video and audio processing cores which can be reused by customers and decrease their design cycles. These IP cores include MPEG - 2, MPEG-4 encoder/decoder for SD analog video standards (NTSC, PAL) and HDTV standards, VBI standards. Digital signal processing cores include digital filters design, audio encoder/decoder