Verification Engineer - Intern Resume San Jose, CA - Hire IT People

OBJECTIVE:

SUMMARY:

Proficient in SystemVerilog fundamentals including Randomization and Functional Coverage.
Proficient in Universal Verification Methodology (UVM).
Comprehensive knowledge in ASIC design flow fundamentals.
Successfully implemented various design and verification projects using Verilog, VHDL, SystemVerilog and UVM.

TECHNICAL SKILLS:

Digital Domain: Verilog, VHDL, SystemVerilog.

Scripting: Perl.

General: C, C++, Assembly level.

WORK EXPERIENCE:

Confidential, San Jose, CA

Verification Engineer - Intern

Responsibilities:

Coding of test cases and analyzing the test results based on the verification plan for Bus Arbiter design which uses I2C protocol.
Performing Regression and gate simulation runs for the same design.
Currently building SPI verification IP based on UVM.
Built a basic UART verification IP based on UVM.

Confidential, Fairfax, VA

Intern

Responsibilities:

Performed interfacing between host PC and Virtex5 ML507 FPGA board which involved high level C and VHDL coding.
Interfacing was based on Peripheral Component Interconnect Express (PCIe) and Jungo driver.