Senior Staff Verification Engineer Resume

SUMMARY:

10+ years’ solid working experience in IC Verification & Design. Full understanding about IC Verification & Design flow.
Mastery of UVM (Universal Verification Methodology) and VMM (Verification Methodology Manual). Proficiency in System Verilog.
Rich experience in coverage - driven constrained random testbench building. Well trained debugging skills for testbench/C/RTL. Owner of verification task for several complex IPs.
2+ years’ experience in IC firmware development. Knowledge of computer architecture.
Experience in FPGA design and FPGA verification. Some knowledge on emulation.
Highly detail oriented, extensive management experience. professional, excellent teamwork

TECHNICAL SKILLS:

Program Language: System Verilog, VerilogHDL, VHDL, Matlab, C, C++, Perl, TCL

Verification Methodology: UVM, VMM, and OVM

Tools: Incisive, VCS, DVE, Irun, Leda, Design Compiler, GDB, GCC, Makefile

Interface & Bus Protocol: AXI, AMBA, SATA, PCI, USB.

PROFESSIONAL EXPERIENCE:

Senior Staff Verification Engineer

Confidential

Responsibilities:

MTS Verification Engineer

Confidential

Responsibilities:

Verified SATA (Serial Advanced Technology Attachment) at the block and system levels
Synopsys SATA VIP (Verification Intelligent Property)’s integration and creation of SATA test cases
Design quality control through regression clean-up

Senior Hardware Engineer

Confidential

Responsibilities:

Built verification environment based on OVM (Open Verification Methodology) for 10G Ethernet systems.
Owner of c model maintenance and integration.

Verification Technical Manager

Confidential

Responsibilities:

Tech lead of 3G modem’s block-level verification
Supervised verification of several IP, from testplan creation to design sign off.
Worked around tough issues like hard solver in generator and coverage definition for complex cases.

DSP Firmware Engineer

Confidential

Responsibilities:

Developed DSP (Digital Signal Processor) firmware for VDSL (Very-high-bit-rate Digital Subscriber Line) system
Implemented digital signal processing algorithms used in VDSL physical layer.
Self-defined DSP engine and relevant RTL design.

FPGA/IC Design Leader

Confidential

Responsibilities: