SUMMARY:

• Ten plus years of engineering and management experience in high - tech industry.
• Strong communication skill and vendor management: NPI (New-Product-Introduction) lead throughout the production and qualification cycle.
• Project management experience (SCRUM and waterfall) with PM from UCLA (2016).
• Hands-on experience in both electronics and software development.

TECHNICAL SKILLS:

Technology and Tools: Cadence Virtuoso, AIUM, Incisive, Spectre, APS, Ultrasim, amsDmv, and UVM - MS. Mentor Graphics Modelsim, Questa, and ADMS. Synopsys VCS and HSPICE. Behavioral modeling for PLL, ADC, DAC, transceiver and other mixed-signal IPs. Digital verification in OVM/UVM. SystemVerilog, Verilog, Verilog-AMS. C programming, PERL scripting. Unix/Linux/Windows ATE Agilent 93000 and test program development RF IC design and verification (academic) Project management with MS Project/Excel/Word/PowerPoint.

PROFESSIONAL EXPERIENCE:

Confidential, San Diego, CA

Full-chip validation engineer (contract)

Responsibilities:

• Top-level SOC digital verification for the most advanced audio codec chipset.
• UVM test and assertion development for functional and connectivity verification.
• Gate-level simulation and debug on all the required corners at the full-chip level.
• Validation for register access arbitration among multiple hosts with different bus protocol (PIF, SLIMbus, I2C, AHB)
• Functional and code coverage closure.

Confidential, San Diego, CA

AMS verification architect

Responsibilities:

• Worked on two ASIC driver chips for leading MEMS display technologies: Mirosol and DMS MEMS technology
• Architected the chip-level mixed-signal verification environment for display driver chip, with Cadence UVM-MS integration and SPICE capability.
• Behavioral model development/validation in Verilog-AMS to improve simulation throughput and full-chip sign-off.
• Develop and release behavioral models to digital verification team.
• Hands-on knowledge in architecture of display driver, C-PHY and DSI MIPI.
• Chip-level test plan creation and coverage hole identifications.

Confidential, San Diego, CA

Mixed-Signal Verification Engineer

Responsibilities:

• Core member of digital verification team for the very first internally developed USB3 PHY IP from Qualcomm.
• Integrating third-party VIP (Synopsys) for end-to-end verification.
• Executed test plan creation, RTL/gate level simulation, assertion and coverage closure in order to achieve the highest order of tape-out quality.
• Support design and post-silicon test team for the initial bench bring-up, verifying power-up sequence and operational mode.
• Bring up Cadence AIUM for AMS (Analog Mixed-Signal) verification flow as part of product development flow for USB3 and DDR3 PHY.
• Worked in highly globalized work environment, collaborating with various design/verification teams from India, Israel and US to achieve demanding milestones.

Confidential, Sunnyvale, CA

Designer/Product Introduction Lead

Responsibilities:

• Core member of RTL design team for LF4460 HD Video Frame Buffer
• Analog verification of OTP-based fusing scheme for SRAM memory redundancy, simulated in Synopsys Hspice and Nanosim.
• Fuse array behavioral modeling with Verilog for much improved simulation performance.
• Implemented memory repair algorithm in C as part of the production program for LDI SRAM products.
• Product lead for DRR module product line from product definition to qualification following stringent Military specification. Tasks including:
• Market research and collecting customer feedback.
• Cost analysis (production).
• Perform evaluations on test platform and qualification standard
• Select test equipment suppliers and negotiate pricing.
• Project management to maintain schedule and cost.
• Develop production and qualification flow
• Perform actual product testing and debug
• Post-silicon characterization and test program development for high-speed DDR2 and DDR3 modules with Agilent 93000 tester. Perform production program audit and yield analysis to improve production quality.

Confidential, Sunnyvale, CA

Summer intern

Responsibilities:

• Bench characterization for ADC and DAC.
• Testcase creations for watch-dog timer of the micro-controller in Native-Sim environment.

Confidential, Chandler, AZ

Pre-silicon RTL validation intern

Responsibilities:

• Performed Full-chip simulation for Intel 955X Express Chipset with DDR 2 and PCI express capability.
• Executed test plans to reach RTL milestones for successful tape-out. Drive each test, simulation environment, and logic issues to closure by coordinating cross-site debugging effort between Chandler and Folsom.
• Perform first-level isolation on full-chip simulation failures, and dispatch the issue to appropriate test owner/designer to root-cause the test issue or logic bug.
• Writing Perl/C-shell script to streamline the RTL test execution and test database management.

Confidential, Tucson, AZ

Software Engineer

Responsibilities:

• Worked as RAS (Reliability, Availability, and Serviceability) representative to provide field support and repair procedures for Fortune 500 corporate accounts. Code and compile schemes for field replacement unit strategy and guided maintenance service.
• Kernel extension developer for IBM Enterprise Storage Server (Shark) specialized in C programming in AIX/UNIX environment.