SUMMARY:

• Sixteen years of experience in telecommunication and semiconductor industry ( Confidential, Confidential, Watkins Confidential and more); broad technical background/experience in failure analysis/reliability including device and defects characterization, root cause of digital/analog device failure, electrical testing, EM, TDDB, HCI, NBTI/PBTI, ESD/latch - up, reliability simulation using Cadence and Synopsys tools; quality assurance and control, improvement of product yield, knowledge in analog circuit design using Cadence Spice tool, involvement of digital microcontroller/logic design.
• Six years of experience in development of semiconductor process including Cu integration, CVD, high density plasma CVD, magnetron sputtering, and thermal diffusion.

PROFESSIONAL EXPERIENCE:

Confidential

Senior Engineer

Responsibilities:

• Performed technical work and managed a testing/failure analysis/reliability/ dept. including FIB, TEM, SEM, SAT, X-Ray radiography, Advantest tester, EMMI/OBIRCH, RIE,etc with more than twenty engineers and technicians for a 70000-8inch-wafers of fab.
• IC reliability simulation using Cadence tools based on BERT and ARET ( EM, HCI, TDDB, oxide breakdown, NBTI). Performed and managed reliability test ( EM, HCI, TDDB, NBTI, GOI, ESD, and latch-up) on JEDEC standard. Using Cadence (SPICE) tools to analyze analog amplifier, converter, microcontroller, BiCMOS circuits, logic gate array; etc.
• Involvement of yield enhancement for all products (Yield Chart, sorting of bin modes, pare to of defective modes, plan of process adjustment). Participated in customer engineering, quality assurance, and QC management (/PCCB / EAR /SPC /DOE /FMEA /IQC /VQC / OQA / Calibration / C/R environment). Strongly involved with design service, circuit modification, integration and advanced module development.

Confidential

Senior Engineer

Responsibilities:

• Performed technical work, and managed a failure analysis/reliability labs/department with more than twenty engineers and technicians; performed technical guidance; evaluated and purchase failure analysis and electrical testing instruments including TEM, SEM. participated in internal quality audit plan with TS16949 qualification.

Confidential, Tempe, AZ

Senior Staff Electronic Engineer

Responsibilities:

• Worked with integration/process/device groups to develop FEOL and BEOL for Hip7(Cu/low-k/SOI), SiGe HBT, split gate flash memory, Magnetic RAM, BiCMOS, LDMOS, RF bipolar devices; involvement of device parametric testing and datalog analysis, identification of electrical failures, characterization of failed devices by analytical instruments (FIB, SEM, TEM, SAM, SIMS, XRD, AFM), determination of corrective actions (with process group) using FMEA, and of more than 30% of yield improvement.
• Involved with problem solving for package reliability and failures (using SAM, SEM, FIB); major problems included bump (PdSn based) cracking and voiding for Flip-Chip mount; non-sticking bond pads due to contamination, galvanic corrosion for Al (Cu) pads, voiding on Si/Ni/Cu bonding for RF bipolar and LDMOS, and backside metal peeling (Au/Ti/TiN) on PHEMT and EMODE die package.
• Participated and be trained in reliability data analysis using Weibull and log-normal statistics; familiar with accelerated testing and device reliability (electromigration, stress voiding, hot carrier degradation, and TDDB).
• Familiar with LPCVD poly-Si, APCVD Si glass, PECVD nitride, PVD metal films, RTA, and wet and dry etch.
• Be trained in ISE TCAD (Genesis) and parametric testing using Confidential Standardization of Parameters and Measurements (SPAM).

Confidential, Santa Cruz, CA

Process Engineer

Responsibilities:

• Design of WJ2000 high-density plasma CVD system and development of process flows; worked with deposition of nitrides, Si oxide and low-k films; implemented and developed intermetal dielectric process modules and WJ-2000 control system; evaluation of dielectric film filling for trenches with different aspect ratios.
• Performed experiments for measurements of thickness, uniformity, stress, and wet etch rate for films; established data base with SPC chart, demonstrated process modules and collected data for potential customers.

Confidential, Urbana, IL

Research Scientist

Responsibilities:

• Development of Cu-In-Se (CIS) and microcrystalline poly-Si solar cell films by magnetron and PECVD process.
• Evaluation of microstructure and growth of these solar cell films by TEM, XRD, SEM, and AES, and SIMS. Fabrication of multilayer solar devices.
• Performed electrical testing of solar cell devices such as open circuit voltage and short circuit current and so on.

Confidential, Lafayette, IN

Post-Doctoral Research Associate

Responsibilities:

• Development of high-temperature superconducting films by sol-gel process; fabricated metal film contacts for superconducting films using e-beam evaporation and plasma sputtering deposition processes. Also, used HRTEM to characterize MOCVD GaN and superconducting films.

Confidential, Chicago, IL

Graduate Research Assistant

Responsibilities:

• Development of high temperature superconductors; synthesis of Y-Ba-Cu-O and Bi-Sr-Ca-Cu oxides by sintering, zone melted, and rapid quenching; investigated relationship between microstructure, magnetic flux pinning, and critical-current density.