SUMMARY:

• Experience in troubleshooting, debugging, fault diagnosis of x86 based planars storage Serial attached SCSI adapters
• Mentor Graphics viewlogic/viewdraw and Orcad/ Pspice/Matlab/Simulink/ for schematic entry/simulation
• Cadence allegro SI/SIGXP, MentorGraphics Hyperlynx, ANSOFT HFSS for signal pre/post layout/simulation
• Various FPGA/CPLD tools from Xilinx, Altera, Cypress, Aldec, Lattice and High speed oscilloscopes from Agilent for signal integrity
• Languages known - x86 assembly, VHDL, C.

SKILLS/TOOLS

Bus Knowledge: ISA,LPC,PCI/PCIX, PCIe, SCSI, SAS, Xeon System Bus, QPI

OS knowledge: DOS, Windows, Linux

EXPERIENCE:

Confidential, San Francisco Bay Area, CA

Server Validation Engineer

Responsibilities:

• Board design schematic veification,system level testing on x86 platforms.
• Server platform validation with sound understanding of CPU and other critical components.
• Interface with outside vendors and internal hardware, mechanical, power, thermal and software engineers to understand system architecture to develop and execute the test suites for various architectures.
• Work with the Vendor management team to evaluate components and provide inputs for reliability and feasibility.
• Knowledge of analog and digital circuit - board design experience.Hands on experience on lab equipment, like oscilloscope, logic analyzer, digital power meter and voltage regulator tuning.
• Validation experience of high speed test debug experience (PCIe, 10G, SAS, SATA, USB).
• Testing of server internal modules such as IPMI managements and kernel and PXE .
• Use linux bash shell script and capability of composing automation test script.
• Hands on experience on stress test, stability test and reliability test.
• Create automated test infrastructure, through the use of scripted languages and remotely controlled test equipment.
• Generating test plans and document them.
• Execute test according to plan, while keeping a through procedural record and data log.
• Develop and publish test reports and communicate findings to team members Diagnose and root cause of system failures and isolate the components / failure nodes.
• Respond on an as-needed basis to emergencies and provided remedy for catastrophic failure events

Confidential, Greater Boston Area, MA

Senior Hardware Engineer

Responsibilities:

• Hardware design validation of various high available Gen3 SAS/PCIe storage enclosures supporting Confidential Romley/Grantley family of processor based integrated compute nodes.
• Understanding of the complex storage infrastructure to implement logic design,debug and implementation of storage enclosure services and storage management functions of enclosure services on FPGA with verilog HDL and SES validation.

Confidential, Research Triangle Park, NC.

Advisory Development Engineer

Responsibilities:

• Design of high performance, high speed server board and RAID controllers schematics,validation of the logics, high speed programmable logic design using HDLs, design and validation of chipsets and systems.Design of schematics for storage subsystem, PCI/PCI express subsystem implementation,U320 SCSI,SAS(Serial Attached SCSI) implementation and signal integrity work
• Worked on reference design for 12Gb SAS RAID down solution (LSI Logic 3004/3008) for next generation PureFlex systems and RAID up solution for PureFlex /modular server LSI 3108 cache design.
• Worked on TMM (Transportable memory module TMM) (DDR3 - 1333Mhz/512MB/1GB/2GB) for the Gen2 SAS HBAs and TMM(Cache- DDR3- 1866Mhz/1GB/2GB) for Gen3 SAS HBAs and their reference designs
• Validation of the backplanes for (Romley EP/EX Pureflex sub systems) covering the RAID portfolio and 12Gb SAS RAIDcontroller/ROMB portfolio for the (Grantley EP/EX) Modular system and Blade portfolios and SW RAID solution to support .
• Worked on design validation of the backplanes for the PureFlex Mezz cards (PCIe based HBAs)to support 2/4 drives 1.8 SSDs/2.5 drives.Responsible for SI on the solution, very complicated due to extended lossy cables and high-speed SSDs
• Focused on new 12Gb designs.Completed the schematics reference design for memory subsystems for 12Gb adapter.
• Worked on reference schematics for RAID-down solutions on blades and ITEs(PureFlex) using LSI logic s 6Gb 2004/2008 chipset. This supported the transition to LSI s new devices
• Provide guidance to system teams on adopting the design, reviewed implementation, and guided parts selection. I also provided reviews to teammates on PCIe Host Bus Adapters designs and PCIe mezz card for flex systems working to learn new designs and new products and ensuring spec compliance (i.e., SAS2 and PCI gen3 spec).Support Gen3 PCIe/Gen2 SAS adapter for PureFlex systems involving bring up and testing.Worked on technical understanding throughout in solving these issues, debugging and modeling new designs and HDDs
• Ensure solid design practices and clean signals on HBAs, backplanes, and HDDs.Supporting field issues for PE as well, including an issue on 1-U high volume servers.Provided engineering support and design for HDD Backplanes, supporting our System x products.
• Able to successfully work through and deliver the four different configurations of
• I2C scsi enclosure processor(SEP)based backplanes. These activities includes such as schematic entry, feedback on PD, bring up and testing of boards including signal integrity as well as test support.
• Worked on the SGPIO SEP based backplanes and conducted bring up on the first pass cards as well as provided feedback on the 2nd pass of these card. These cards remained active in development.
• Provided Lead Engineer support on the Vitesse ASIC 6250 ROC (raid on a chip) for ROMB implementation and later transitioned onto the HDD Backplanes, developing the next generation of products.Work outlined above included support for numerous system releases and associated challenging bring-up, debug activities.
• Designed subsystems such as SCSI using Adaptec 7902 for ultra320 and the ROMB(Raid on Motherboard) using Confidential Dobson IO(80332) processor. Implementation included various bus implementation such as Gen-1 PCIe from MCH to Dobson, PCIX 1.0(133Mhz) from Dobson to Adaptec 7902,Peripheral bus for Dobson to raid flash, NVSRAM and DDR333Mhz from Dobson to cache moudule.Work also involved implementation of CPLD for various miscellaneous logic for Dobson emulator, reset logic and battery back up for transportable memory work included implementation of various power regulator circuits for different voltage rails for Dobson such as 1.3V for Dobson core, 2.5v and 1.25v for Keywest DDR333Mhz, 1.5v for PCI express and 1.8v & 2.5v for SCSI
• Adaptec 7902.Familiarization with Confidential chipsets architecture such as MCH Lindenhurst, Dobson, PHXD, to implement work around for various erratum for different stepping of the chipset and also layout related issues involving the chipset at various stages of early design.
• Work on developing x-series two way servers x345 and x3650.Work involved understanding the SCSI ultra320 bus .
• Designed the SCSI subsystem of the 2- socket rack server planar. It was the building block owner U320 SCSI subsystem for the 2-socket Tower/Rack servers.
• Resolved several technical issues related to the LSI SCSI chip different steppings .Developed a good working relationship with the LSI engineering team while working through issue
• Work on developing x-series 2-way high volume servers.
• The work involved understanding the PCI-X subsystem interms of form factors, performance and bus loading.
• Involved first pass board bring up of the server planar.
• It was the building block owner PCI subsystem for the 2-way Tower/Rack servers.
• Resolved several technical issues related to defects related to PCI exerciser related in general interfacing with various test teams while working through issues.
• Logic design for the I2C expander several of those used for system management subsystem for alerts and light work involved bring-up System management subsystem down on the work involved schematic, layout and logic design and go thru various test cycles to fix hardware/software/firmware issues.

Confidential, Folsom, CA

Hardware Engineer

Responsibilities:

• Silicon validation and to support validation effort to develop validation tools were PCIx based adapters with FPGA with logic embedded to exercise the protocols targeted
• Architecture definition of FPGA for SMBUS protocol validation, coding, simulation in Altera maxplus II, and develop exerciser for that.
• Design, bring up, debug of the 430TX and 440BX chipset based motherboards and validation of the north/south bridge
• Design of microarchitecture for PCI interface in Camino chipset
• Development of the firmware, software and FPGA for stress test for Power management features of included various suspend, power down and resume states of 440BX and CPU

Confidential, Austin,TX

Contractor

Responsibilities:

• The work involved design of RS - 6000 based motherboards.
• The work involved running various device drivers under DOS,WINDOWS,AIX to locate the bugs in the mother boards.
• To implement various work arounds to avoid sillicon bugs and to provide feedback to software development team to update device drivers for newer updates of sillicon,to fix any timing issues and to implement temporary reworks to avoid sillicon bugs.
• To design glue logic using various HDLs to improve cost and performance of the boards.