SUMMARY

• Over 7 years of experience in ASIC Verification, RTL Design including design specification, RTL coding, simulation, synthesis, logic equivalence check and power analysis.
• Well versed with System Verilog and progressive experience with UVM test methodologies.
• Strong expertise in IP Verification, SV Assertions, Functional Coverage and Low Power Verification.
• Strong knowledge ASIC/ FPGA pre silicon verification with Full constraint random testing, coverage based verification.
• Expert in handling bunch of Test cases, reporting the bugs, running regression testing and coverage.
• Hands on experience with clean room and fabrication process. Knowledge in Designing Nano scale sensors and exploring new devices.

TECHNICAL SKILLS

HDL: Verilog, VHDL, System Verilog.

Hardware Platforms: Basys, Basys 2, Spartan 3E, Spartan 2, Vertex5, Arduino.

IEEE Protocols: PS2 keyboard, 8bit VGA

BUS Protocols: AXI, AHB, APB

EDA Tools Cadence: SOC Encounter, RTL Compiler, Virtuoso, Layout XL, Spectre

Synopsys: Design Compiler, HSPICE, VCS

Xilinx: Xilinx ISE, Impact

TCAD Tools Synopsys: Sentaurus Process, Sentaurus Device, Sentaurus Structure

Programming Languages: C, Assembly Language, Embedded

PROFESSIONAL EXPERIENCE

Confidential

Graduate Research Assistant

Responsibilities:

• TCAD based simulations of 3D Image sensor, integration of sensor and circuitry in a single chip.
• Master of Science thesis on “Exploration of 3D Nanowire Image sensor and circuitry to enable logic and sensing in single chip”.
• New Mercury Cadmium Telluride Nanowire based photo detector has been implemented horizontally; Simulations have been carried out using optical model.
• Optical generation has been measured by using Synopsys TCAD and found to be efficient.
• Design of Junction less Nano wire transistor in Sentaurus Process
• Boron doped silicon horizontal Nano wire of 20nm wide and 100nm long has been grown on SOI wafer.
• HfO2 and Polysilicon have been deposited for gate formation at center of Nanowire.

Confidential

ASIC Verification Engineer

Responsibilities:

• MIPI - CSI2 Rx IP Verification CSI2 is a Camera Serial Interface which interfaces to Camera via CSI2-Tx and D-PHY Interface. The D-PHY protocol defines the signals, timing, and functionality required for efficient communication Between Tx and Rx interface.
• Developed the IP LEVEL BENCH for CSI2 using UVM. Created verification plan, test plan to cover all the cases.
• Coded Test cases to verify the functionality of CSI2.
• Setup the COVERAGE MODEL to check CODE COVERAGE and FUNCTIONAL COVERAGE and documented the Test Plan.
• Setup the MONITOR and SCOREBOARD to check the data integrity Between the RTL and Bench.

Confidential

Verification Engineer

Responsibilities:

• Development of I2C: Developed the Agent (driver, monitor and Sequencer) using System Verilog and implemented using UVM.
• Developed the detailed test plan and wrote the test cases and verified.
• Verified the Preliminary functionality of DUT. Implemented all blocks of SV UVM VE.
• Complete Functional Coverage measurement including stimulus condition and device response.

Confidential

Digital Design Engineer

Responsibilities:

• Performed code debugging of various IEEE protocols, FPGA Prototyping and verification of the IEEE protocols like audio and video protocols.
• Implementation of 8 bit VGA and PS2 keyboard with the BASYS FPGA kit.
• VHDL codes have been synthesized using Xilinx ISE 13.7 UCF has been mapped to BASYS kit.
• Recognized character generated by keyboard, displayed character/ screensavers/ patterns on VGA.
• Design, Verification and implementation of Car Race game and ping pong game on the hardware SPARTAN 3E by configuring FPGA with PS2 keyboard and VGA monitor.
• VHDL codes have been developed to display a color pixel. Car Race game and Ping pong game specification is made and designed the game in VHDL coding.
• Design is debugged and verified by monitoring signals using Mixed signal Oscilloscope. Series of 8bit VGA data is verified using Logic Analyzer.

Confidential

Project Engineer

Responsibilities:

• Worked for the development of new models for low power full adder and ALU designs implemented those designs in Cadence Virtuoso and evaluated the performance.
• Master of Technology thesis on “Low-Power-Area ALU design using proposed low power full adder design”.
• ALU circuit is designed by using proposed low-power full adder designs (8T, 10 T and 12 Transistor designs).
• Several low power techniques have been implemented on ALU circuit, Improved the performance.

Confidential

Graduate Intern

Responsibilities:

• Designed and Verified Black Jack using Verilog HDL on Xilinx Spartan3 Implemented the design using Top-Down methodology approach.
• Used Verilog-HDL, Synthesized using XST (Xilinx Synthesis tool). Optimized the design according to the architectural specification.
• Optimized the design with all the possible constraints. Created the test scenarios and thoroughly verified the design.
• Helped the customers to meet the timing requirements for their design by effectively giving optimized constraints on the Xilinx Constraints editor.
• Debugged configuration issues related to the downloading of the design bit stream on to the FPGA. Helped the team to reach their project goals.