SUMMARY:

• 8 Years of strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG.
• Experience in the design of Xilinx Zynq - 7000 Soc, Spartan3E, Lattice LFXP2-40E, and LFXP2-30E & Altera Cyclone III FPGA Boards.
• Good Knowledge of ASIC design tools and process flow
• Proficient with C/C++, Verilog HDL, VHDL and System Verilog
• Good knowledge in simulation tools Cadence, Questasim, & Active HDL simulators
• Strong experience in design implementation tools Xilinx Vivado, ISE design flow & ChipScope Debug Tool
• Developed test environment and set a test plan, Coverage group, Functional coverage
• Verification tests based on constrained random achieve verification metrics
• Ability to understand high level architecture and take to implementation
• Good knowledge ASIC IP RTL to FPGA prototyping for lab testing
• Ability to understand and partition design into H/W and S/W components
• Participated in design reviews, Requirement review and Simulation test case review
• Experience with DO-254 Standards, Chain Management & Certification.
• Good working knowledge in MATLAB Tool Kit and DSP signal processing applications
• Expertise with SPICE circuit simulations.
• Proficient in using lab debugging tools such as Logic analyzer, Oscilloscope and current sensors
• Expertise with version control systems (CVS, MKS and DOORS)

TECHNICAL SKILLS:

HDL & SIM TOOLS: Verilog, VHDL, System Verilog, UVM, Cadence Incisive/ NC-Verilog, QuestaSim

SYNTHESIS: Xilinx Vivado, ISE, Altera Quartus, Lattice Diamond, Synopsis Design Compiler (DC)

TIMING ANALYSIS: Synopsys STA

LINT TOOL: Spyglass

SCRIPT & PROG: Perl, TCL, C/C++, Python, LabVIEW

PROFESSIONAL EXPERIENCE:

Confidential, Irvine, CA

FPGA Design Engineer

• Developed FPGA based designs providing communications and motor controls for surface control electronics and Interface modules for aerospace industry for various flight programs.
• Responsible for architecture of the design, RTL design, Synthesis and Bit file generation.
• Contributed product improvement team to support eliminate clock domain crossing issues result in improved timing and performance.
• Participated in design review, provided design changes and bug fixes resulting in successfully completing program.
• Contributed in designing individual modules, Functional simulation, code coverage, worst-case timing simulation and Integrated to the top-level design.
• Supporting multiple projects performing code analysis, timing closure, identifying and resolving problems
• Supported design, Testing, Automation, Validation and Verification
• Interface with functional groups Systems, Verification, Process/Quality
• Involved in technical team coordination meetings in three different regions

Confidential, Sunnyvale, CA

FPGA Design Engineer

Responsibilities:

• Designed SDIO bus Analyzer to detect SD card Initialization module which enable to analyze command, response and data packets. Designing the individual modules and top-level architecture for SDIO implementation.
• Involved in the top-level design using structural modeling of Verilog HDL that includes interconnection of all the internal blocks.
• Developed Time stamps for each command, response and data packets.
• Developed test bench to verify unit level blocks and Top module.
• Synthesized the design to extract the gate level net-list for ALTERA Cyclone III FPGAs.

Confidential

Teaching Assistant

• Understanding the IEEE 802.11 WIFI security specifications.
• Designing the individual modules and top-level architecture for algorithm implementation.
• RTL coding in VHDL for the following modules:
• Design of SMC to handle key setup and key stream generation phases of RC4 algorithm.
• Design of RAMs and FIFOs to handle key data and plain text respectively.
• Involved in the top-level design using structural modeling of VHDL that includes interconnection of all the internal blocks, and their interconnection with application layer on one end and physical layer at the other end.
• Synthesized the design to extract the gate level net-list for Lattice LFXP2-30E FPGA.

Confidential

Teaching Assistant

• Project deals with design of Universal Serial Bus (USB) Transmitter and Receiver protocol implementation that Link layer flow control and transaction level fault recovery are then covered.
• Understanding the USB 2.0 specifications , Designing the individual modules and top-level architecture implementation.
• Design of Token CRC and Data CRC to handle Packet data & Token packet respectively.
• Error detection, Error handling and data flow control
• Involved in Token, Data, Handshake and Initialization Setup via setup tokens and Successful data transactions.
• Involved in the top-level design using structural modeling of VHDL that includes interconnection of all the internal blocks, and their interconnection with application layer on one end and physical layer at the other end.
• Synthesized the design to extract the gate level net-list for Altera cyclone III FPGA.

Confidential

Design Engineer

• Designing the individual modules and top-level architecture of Physical layer block for the PCIe Base 1.1 specifications.
• Frames the TLPs or DLLPs with start and end characters.
• State Machine Control (SMC) Logic design.
• The framed packet is send to the Byte Stripping Logic, which multiplexes the bytes of the packet onto the programmable multiple Lanes.
• Scrambler uses an algorithm to pseudo-randomly scramble each byte of the packet.
• The 8b/10b Encoder encodes scrambled characters into 10-bit symbols and 10-b symbols are converted to a serial bit stream by the Parallel-to-Serial converter.
• Developed test bench to verify unit level blocks and Top module.
• Synthesized the design to extract the gate level net-list for XILINX Spartan 3E FPGAs.
• Involved hardware debugging, Board bring up and Safety critical tests.