SUMMARY:

• Senior firmware engineer with experience in firmware and hardware, emphasizing analysis of engineering problems in the wireless, optical networking, avionics, semiconductor manufacturing and medical device industries.
• Experienced in the implementation of DSP embedded firmware/hardware solutions.
• Strong background in Signal Processing, DSP Algorithm Development, Software Design and Development, Process Modeling, Software Quality Assurance, Verification and Validation.
• Highly skilled communicator who is well versed in all aspects of systems and software design methodologies including requirement specification, project planning, detail design, coding and testing.
• An analytical problem solver with good attention - to-detail and with experience in working with offshore project teams .

TECHNICAL SKILLS:

Real-time Operating Systems: Embedded Linux (OpenWrt), VxWorks, Integrity, Nucelus OS, DSP/BIOS

Bus Architectures: PCIe, Ethernet (TCP-IP/UDP), AMBA, VME, SPI, I2C, RS-232/422/485, USB, GPIB

H/W and F/W Development Tools: Oscilloscope, In-Circuit Emulator, Logic Analyzer, Spectrum/Optical, Spectrum Analyzer, PROM/FLASH Programmer, CPLD Programmer/Synthesis Tool

Wireless Test Equipment: Vector Signal Generator (MXG), Signal Analyzer (PXA/MXA), RF Channel, Emulator, Protocol Conformance Tester (PCT) from Rohde & Schwarz, Anritsu, Anite and Aeroflex

Scientific, Data Analysis and Automation Tools: MATLAB, Simulink, SPW, LabVIEW, Python, Tcl, Bash Shell

Development/Host Platforms: Linux, Windows XP/Vista/7/8, UNIX, DOS, Solaris, SunOS

CASE Tools: Agile/Rally, GIT, Gerrit, JIRA, SVN, Perforce, TFS, Visual SourceSafe, ClearCase, ClearQuest, DOORS, PVCS, Bazaar, Paradigm Plus (OOD tool), Doxygen (C++ document generation tool)

WORK EXPERIENCE:

Confidential, Newport Beach, CA

Wireless Firmware Engineer

• Working in various firmware and systems aspects of interfacing the Baseband Unit (BBU) of a 3GPP cellular base-station to RFICs and Remote Radio Heads (RRHs). Currently involved in development of a FPGA based coprocessor to high-end Intel Xeon processor to offload the baseband Physical Layer (PHY) processing in order to interface to multiple RRHs.
• Prior projects have included development of a unified radio driver for the baseband Physical Layer (PHY) software for the 3G/4G small cell base-station platforms. Using this driver validate the next generation baseband radio interface IP. Position requires knowledge of various 3G and 4G cellular radio standards including Carrier Aggregation (CA) and License Assisted Access (LAA) in WiFi bands (3GPP Release 13) and thorough understanding of the different baseband radio interfaces and PHY processing platforms .
• Currently working in both firmware and systems engineering capacity in development of frontend PHY FPGA board interfacing to multiple RRHs and backend PHY firmware running on Intel Xeon platform. A 10GB Ethernet interface is used between Xeon and FPGA board while Common Public Radio Interface (CPRI) is used to interface the FPGA board to RRHs. The Altera Arria 10 FPGA and RRHs from AceAxis are used in the project. Work involves defining hardware architecture of FPGA board with analysis of frontend 4G LTE PHY processing together with 10GBE Xeon host and CPRI radio interfaces which includes in-band control of RRHs. Position requires knowledge of both uplink and downlink PHY backend software running on Xeon platform, PHY frontend processing blocks on FPGA, high speed serial radio and host interfaces, evaluation of FPGA and existing IPs for RTL development work, etc. Work involves day-to-day interaction with Host Software (running on Linux), RTL/Verilog design and OVM Test-bench verification engineers and working with MATLAB, C, Python and Verilog.
• Designed and developed the firmware radio driver for the front-end baseband PHY software to interface to RFIC for the different 3G and 4G radio implementations. The work involved unifying the existing radio drivers of the different Frequency Division Duplex (FDD) and Time Division Duplex (TDD) teams running on Baseband IC (BBIC) to communicate with Analog Devices AD9361 RFIC. It involved understanding the requirements of both FDD (FDD-LTE and WCDMA) and TDD (TDD-LTE and TD-SCDMA) radio systems, the SPI and JESD207 radio interfaces and the existing radio drivers running on Linux/ARM Cortex-A9 or CEVA-XC323 DSP platforms of the different FDD and TDD radio teams. The driver was written in C and made portable to run bare-metal or under real-time OS on any GPU or DSP platform.
• Using the above unified radio driver framework, currently involved in validation of the next generation baseband radio interface IP which includes the JESD207, high-speed SerDes JESD204B and Digital Front End (DFE) radio interfaces. The AD9361, AD9368 and AD9373 RFIC FMC evaluation boards are used for this validation. Currently validating these IPs at the pre-silicon FPGA level using the Synopsys HAPS-70 prototyping platform. Task involves working with RTL simulation and systems engineering teams in validating these radio interfaces based on performance and various radio use-cases for FDD and TDD radio systems. Validation involves converting Verilog Test-benches to C programs, test vector generation using MATLAB/Simulink model, configuration of baseband IP and RFIC module, automation of loopback tests for bit-exactness, spectral measurements using PXA/MXA and offline data processing using MATLAB and other signal analysis tools.

Confidential, Fremont, CA

DSP Firmware Contractor

• Involved in development of Physical Layer (PHY) firmware to enhance performance of the DSL Customer Premise Equipment (CPE) for the existing VDSL2 modem device platform. The position requires knowledge of both ADSL2+ and VDSL2 technology particularly with emphasis on ANSI hardware implementation.
• Design and implement a receiver echo filter auto-selection algorithm whereby a front-end analog filter is either enabled or disabled for run-time operation based on measured aggregate SNR for each filter setting during training phase. Change the existing VDSL2 CPE firmware state-machine to perform modem training procedures for each filter setting which includes Automatic Gain Control (AGC) and Frequency Domain Equalization (FEQ) trainings and subsequent measurement of aggregate Signal-to-Noise Ratio (SNR) of the demodulated signal over all in-band tones (D1, D2 and D3) for downstream data. Since two training sequences are required to be performed on the periodic DMT signal during Channel Discovery phase having fixed time duration, existing training algorithms are modified and optimized to fit within the allocated time period.
• Work involves board bring-up and characterization of a single transformer CPE board. Single transformer is used for isolation of both receive and transmit paths of the CPE from transmission line. Perform transmitter and receiver PSD (Power Spectral Density) calibration for optimal CPE performance. Implementations of both projects are done on a MIPS32 platform running Nucleus OS RTOS with coding in C, MATLAB and Python.
• Perform unit testing with Line Simulators for various lines condition including noise and bridge taps. Regression and validation tests included various automation tests including TR-114 conformance tests.

Confidential, Sunnyvale, CA

DSP Firmware Contractor

• Responsibilities include hardware bring-up involving analog front-end and baseband hardware, including RFIC testing and calibration. Work on Synchronizer module including Frequency and Time Tracking, fine-tuning of RFIC and AGC parameters, perform Transmit and Sensitivity Tests, etc. Modify and debug CEVA XC321 DSP firmware at various levels of the downlink and uplink PHY processing chain, including uplink Power Control, Timing Advance, PRACH and SRS generation. Work involves extensive development in C, MATLAB and Python.
• Involvement in Layer 1, Full Stack and Conformance (GCF) testing in preparation for IOT, particularly in the areas of power control, timing advance, PRACH and SRS generation. Extensive experience using Agilent oscilloscopes, signal generator (MXG) and analyzer (MXA/PXA), Rohde and Schwarz LLAPI/MLAPI and Anite Layer 1, Full Stack and Conformance Test platforms.

Confidential, San Jose, CA

Principal Software Engineer

• Responsibilities involved lead role in both systems and software requirements definition and software development of a Helmet Mounted Display System. Work involved developing software for Confidential PowerPC MPC74xx running GreenHills Integrity RTOS (DO-178B Certified) communicating with other PowerPC boards over Ethernet (UDP/IP) and a helmet mounted microcontroller (Microchip Tech. PIC16F87XA) over serial RS-485 interface. Work involved defining communication protocols, messaging interfaces, and designing and writing low-level API and driver software interfacing with Integrity BSP and IP Stack.
• Implemented DSP control, filtering and communication algorithms on Analog Devices ADSP2189 and mathematical helmet tracking algorithms and GUI software on PC104 and Pentium-based PC processor platforms.

Confidential, Fremont, CA

Sr. Firmware Engineer/Software Engineering Manager

• Work entailed full product development cycle from product definition, simulation, implementation and validation including NEBS certification.
• Technically lead and manage a small team of software and hardware engineers in developing a programmable optical switch.
• Developed embedded IBM PowerPC (405GP) firmware and Host GUI software for WINDOWS using MS VisualC++ to communicate with embedded processor to control a set of MEMS mirrors to create optical links.
• The PowerPC board implemented control algorithms interfacing to separate Driver and Monitor boards over proprietary CPLD glue logic. Work involved porting firmware from Evaluation Board and addressing various custom board bring-up issues. Some experience with CPLD/FPGA and Synthesis Tools.
• Single-handedly develop Host PC and embedded firmware to control a MEMS device. Developed embedded Confidential MC68HC908SR12 firmware and Host GUI software using MS VisualC++ to run on various WINDOWS platforms. Communication with embedded CPU was done using I 2 C interface to drive a MEMS VOA with analog voltages. Both a Main Controller and Calibration GUI were developed for the Host PC platform.
• Expand an existing DGE module from 26 to 31 channels. Work involved modifying existing Analog Devices ADSP21065 DSP firmware and relevant software on a PC Host. Developed a Tester running on a PC platform to test the DSP board through the DPRAM interface. This was achieved using a 96-channel PCI-DIO board by National Instruments. Extensive experience with GPIB, PC Serial & Parallel Port interfaces.

Confidential, Fremont, CA

Software Project Lead

• Design and develop software as lead engineer for a laser based eye-corrective surgical equipment for the medical industry. Interface with various groups internally including Sales, Marketing, Field Service, QA and Manufacturing.
• Developed software to enhance performance and calibration of various hardware subsystems. Development encompassed all levels from GUI to device drivers, including a Pentium Host running NT interfacing to Intel 8032 embedded processors through a DPRAM interface. Host software was developed using VC++, MFC, along with ActiveX and DAO. The embedded firmware was developed using KEIL development tools.
• Worked on next generation laser control system based on a PCI dual-processor Analog Devices ADSP21160 DSP board by Confidential . Work involved interfacing with a PC Host and analog input/output PMC modules.
• Work involved software development under stringent FDA and ISO guidelines leading to successful FDA audit.

Confidential, San Jose, CA

Software Project Lead

• Design and develop real-time embedded control software for a semiconductor lithography machine. Lead a group of engineers and provided interface to various internal groups including Marketing, Field Service, Applications and Manufacturing. Responsible for coordinating various software releases and passing Audit.
• Supervised engineers in developing an improved wafer focus subsystem using various wafer mapping techniques. Work involved project planning, technical supervision, test coordination, validation and release.
• Designed and coded wafer alignment algorithms in C/C++ and MC68xxx assembly on Tornado/VxWorks and VRTX platform resulting in improved wafer alignment/overlay performance. Implemented distortion correction algorithms for an optical alignment subsystem; yaw, pitch and roll compensation for a XY Stage alignment subsystem.
• Developed TCP/IP socket based client-server communication software between VxWorks target & UNIX Host. Work involved writing requirements, design & test specification documents.
• Worked on an enhanced reticle and wafer handling subsystem using Genmark automation tool.

Confidential, Issaquah, WA

Software/Senior Software Engineer

• Develop real-time embedded firmware and device drivers for a medical ultrasound system. Work in the area of Doppler ultrasound encompassing entire R & D life-cycle - algorithm definition, DSP processor evaluation, computation load estimation, memory requirements analysis, and implementation involving software design and development.
• Developed signal processing algorithms, performed simulations under SunOS/Solaris, MATLAB and SPW platforms for the next generation Doppler ultrasound system.
• Designed and developed real-time software for a Confidential 68040 VME Board running VxWorks RTOS interfacing to signal processing boards containing floating-point Analog Devices ADSP21020 DSPs. Developed low-level device driver API under VxWorks to interface high level application software to DSP firmware.
• Performed extensive evaluation of floating-point TI TMS320C31 DSP for both single and multiprocessor evaluation board platforms. Experience in various aspects of TI floating-point DSP implementations.
• Developed both host system software on Confidential 68000 running VRTX RTOS and DSP firmware on fixed-point TI TMS320C25 DSP platform to enhance the performance of a legacy Doppler system. Developed both DSP signal processing and communication firmware to interface to the VRTX host including extensive debugging using DSP Simulator and In-circuit Emulator and Logic Analyzer. DSP algorithms included Audio Reconstruction, Spectrum Averaging, FFT, FIR, IIR and Median Filtering. Verification included automation scripts in Bash Shell programming.
• Developed software meeting Good Manufacturing Practices (GMP) required by the FDA & ISO 9000 standard. Formal training in Object-oriented Analysis & Design Methodologies and Fagan Inspection of software.