Website Designer Resume SIUE - Hire IT People

CAREER OBJECTIVE To obtain a full-time or part-time position as ASIC/FPGA Verification Engineer EDUCATION

Master of Science,Electrical and Computer Engineering
Bachelor of Engineering,Electronics and Communication Engineering

EMPLOYMENT HISTORY

Website DesignerConfidential SIUE Feb’10–Dec’10

Responsible for the website design and maintenance
Assisting the director of MMRin his administrative tasks
Enhanced my leadership skills by organizing meetings

Tech SupportConfidential SIUE Oct’08–Dec’10

Assisting in the trouble shooting of the student and faculty laptops
Publishing the lecture recordings onto the blackboard
Provided exceptional contributions to the customer service
Developed a complete understanding of the technology provided at the School of Pharmacy

ASIC/FPGA Verification EngineerConfidential Oct’05 - July‘08

Programmed test cases and test benches in VHDL and Verilog for different projects
Developed scripts in Python, PERL and Shell for automation of simulation and compilation processes
Performed the code-coverage analysis and functional verification of the design
Documented the verification plans following the standards of Wipro
Good understanding of digital logic and circuits, as well as processor architecture concepts and programming
Functional knowledge of Unix/Linux, C/C++, and Perl

TOOLS AND TECHNOLOGY

Operating Systems
MS-DOS, UNIX, Linux, Windows

Programming Languages
Shell, Perl, C, C++, Java, HTML, Awk, Python, Verilog,VHDL,Matlab

Packages
MS-Office, Visual Basic, luminis

CAD Tools
Virtuoso Schematic Editor, Cadence Virtuoso Analog Environment, VerilogXL, NC-Verilog, Virtuoso Layout Editor,
Specman,Modelsim.

RELEVANT COURSE WORK

Courses done:Digital VLSI Design, CMOS RF IC Design, CMOS Analog Integrated circuits, Advanced Digital Systems Engineering, Mixed Signal Design, Linux/Unix for programmers, kernel developers and administrators.
PROJECT EXPERIENCE

Designed an 8-bit arithmetic multiplier TSMC (Taiwan Semiconductor Manufacturing Company) 0.25� process using transmission gates, optimized in terms of area and power consumption which produces 16-bit output.
Designed a bandgap voltage reference (1.2xx Volts) with 2 PTAT (Proportional-To-Absolute-Temperature) current sink outputs(1�A and 10�A)using the TSMC 0.5� process and tested at all the three process corners- Temperature, Worst Case Power and Worst Case Speed.
Designed an Operational Transconductance Amplifier using the TSMC 0.5� process which can be used as an integrator in Sigma-delta modulator and verified at all three process corners -Temperature, Worst Case Power and Worst Case Speed.
Designed a class F amplifier which generated a power of 2W into 50& load. The center frequency is 1 GHz with 100 MHz bandwidth and power supply is 5V.
Designed a Student Educational Processor emulating RISC(Reduced Instruction Set Computing) processor using Verilog.
Developed a testbench for the functional verification of DMAC (Direct Memory Access Controller) and ICU(Integrated Control Unit) blocks of 6102 SOC(System On Chip).
Developed testcases in VHDL, shell scripts for compilation and simulation for system-level verification of XtremeData’s XD1000 and XD2000.
Developed SPI (Serial Parallel Interface) BUS module of BOOST RF IP in VHDLand wrote testcases in Python to test it.
Developed testcases for verifying audio codecs using IMA (International Multimedia Association) ADPCM(Adaptive Differential Pulse Code Modulation) and 2D DCT(Discrete Cosine Transform) algorithms.
Developed a custom low power, batteryoperated singlechannel Application Specific integrated Circuit (ASIC) thatcan be used in a BrainControlled Interface (BCI). It can be used for recording neural signals from the surface of the brain.

CERTIFICATIONS

Cisco Certified Network Associate.

VOLUNTARY ACTIVITIES

Active member of Student Leadership Development Program (SLDP) at SIUE.

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