Design Verification Engineer Resume

OBJECTIVE

Design verification engineer with deep experience in Verification Tools, Methodologies and Logic Design as well as with strong understanding of Object Oriented Programming.
Strongly self - motivated to keep learning and apply in real-life application

TECHNICAL SKILLS

Extended courses: Computer Network, Computer Architecture, Finance, Operations, Marketing, Accounting, Economy, Organizational Behavior, Web Design, Oracle 10g PL, C/C++ Programming, Java Programming, C#, Python

Conference Paper: Publication (Saturation Throughput Gain in Fixed Multiplexing Radio Networks with Cooperative Retransmission Protocols) in 2006

PROFESSIONAL EXPERIENCE

Design Verification Engineer

Confidential

Responsibilities:

Verify Register Clusters in 3 chip sets (5G Network) in UVM and System Verilog simulation
Make a testplans and create testcases, find the root of cause of problem and debug the failed cases
Write C-Shell Scripts and Perl to create tests, run regression simulation, check the status of all register read and write through analog and digital environments

ASIC Verification Engineer

Confidential

Responsibilities:

Developing testcases and updated testbenches in UVM and System Verilog on module simulation
Found and fixed some bugs in both testbenches and RTL
Developed random and direct critical tests to ensure full feature coverage

ASIC Verification Engineer

Confidential

Responsibilities:

Developing testcases and updated testbenches in UVM and System Verilog on module simulation
Focus on buck (voltage stepper up and down), misc(register-in and register-out) and GPIO
Finished functional verification and gate level simulation on five modules ( Digital module and Analog Wrapper)
Implemented SV assertion on logic checking, connection and DFT

Senior ASIC Verification Engineer

Confidential

Responsibilities:

Developed and created the testcases and testbenches in OVM and system verilog
Found and fixed some critical bugs in both testbenches and RTL using VCS and DVE
Managed regression tests on PCI Express - MODPHY and MMP (40 overall testcases)
Verified Power Up and Down OVM Sequences inside the chip (Common and Data Lane)
Responsible for developing test plans, testbenches and testcases in module Debug Master Controller and Performance Streaming
Developed random and direct critical tests to ensure full feature coverage
Used OOP skills (system verilog and C++) and applied SV Assertions
Increased Code Coverage from 70% to 96% and functional coverage from 60% to 98%

Perl Developer and Web Programmer

Confidential

Responsibilities:

Created PERL scripts to extract data in log files and display performance metrics on web site
Maintained client and server scripts to monitor RNC, MSC and MGC (daily and hourly)
Used Expect, Linux B-Shell, TCL, HTML, PERL, JAVA and Perl Module
Planed, scheduled, redesigned and maintained Web Page using HTML, CSS and java-script.
Rewrote the PERL code to interface with HTML Web Page

ASIC Design and Verification Engineer

Confidential

Responsibilities:

Defined and developed verification plans for DUTs and applied object-oriented skills in developing and designing e-Reuse testbenches and testcases(80+) in Specman for verification
Responsible for developing and debugging, testing and running simulation
Found 50+ bugs in overhead bytes handling and pointer processing (STS payload)
Run regression tests using perl scripts for 150 tests and displayed the total results using XML
Applied Object Oriented Design in C++ to create SONET Overhead (TOH, POH, VTTOH, VTPOH) and SONET Payload Data ( SPE, VTSPE) test modules.
Developed test cases to verify STS Pointer Processors, Loopback &VT Pointer Processors
Found 30+ bugs in Pointer Processors, Overhead Processors and top level simulation

IC Design Engineer

Confidential

Responsibilities:

Wrote the Technical Requirement Specification document. Worked on 0.13 um and 0.18 um Technology Library. Created the DC SHELL synthesis scripts.
Compiled and created db for memory and RTL code. Use Design Analyzer to analyze and find out of the timing problems.
Successfully accomplished the Synthesis of the whole chip (1.6 M Gate) by using both top-down and bottom-up methodology. Achieved the time requirement by using the correct constraint values.
Developed and designed the Framer RTL in the Add-Drop MUX by VHDL. Simulated and verified the RTL model by ncvhdl.
Redesigned the Pointer Processor and made it configurable.
Completed all regression tests on both RTL and gate level simulation.
Wrote ARM 925 assembly code to verify instruction cache, data cache, and co-processor
Designed and verified the Bus Controller to interface ARM 925 with the peripherals
Applied liquid Crystal Technique to locate the defect and used high-powered electron microscope to find the cause of the defect.

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