Senior Mask Layout Designer Resume San Jose, Ca - Hire IT People

PROFESSIONAL SUMMARY:

Mask Layout Designer with over 30 years of experience in Full custom IC Layout.
Created layout for high speed Receiver and Driver Chip including IO pads and their ESD circuitry, RF, Analog and Mixed Signal blocks, Mixers, Bandgaps, Amps, ADC’s and DAC’s Switch Caps. Building layout with Clones and Group configuration.
Cadence - Virtuoso, Virtuoso XL, Knowledgeable in device matching, pitch matching, balancing, and shielding of critical devices, differential signal routing. Able to independently perform efficient debugging of Calibre verification results using RVE with ability to implement timely layout corrections of results.
Experience with Floor Planning of Blocks, Standard Cell creation of CMOS, BiCMOS and PCELL devices and Finfet design process.
UMC 90nm, 65nm, 45nm, 40nm, 22nm, 18 and 16nm Finfet CMOS processes.
I easily integrate into existing project teams and work with other contractors or direct employees.
Self-motivated, attention to detail, good communicator with team.

PROFESSIONAL EXPERIENCE:

Senior Mask Layout Designer

Confidential, San Jose, Ca

Responsibilities:

Worked on a dual process to satisfy both UMC and Toshiba 40 - 45nm CMOS processes. Layout of the Clock and ALU section, this included several banks of memory cells. Layout of Opamps, differential pair and mixer cells. Tools used Cadence Virtuoso XL. Layout area with 10 layers of metal. Attention to shielding critical nets, All the metal and gates had to be on grid, and follow a Data Path scheme. Matching of devices. The block had 4X the number of transistors, and took up ¼ the Area, as the previous version.

Sr. Mask Layout Designer

Confidential, Bothell, WA

Responsibilities:

Completed 4 Chips, Two Standard CMOS Mixed Signal, And Two Analog/Digital Micro-Broad beam Former. It was a High Voltage 80 Volt process, the analog circuits are 1-10MHz range. Logic circuits go as high as 100MHz. Triple Well Mixed Signal Design. Worked on Low Voltage DAC’S and Switch Caps.

Senior Mask Layout Designer

Confidential, Campbell, CA

Responsibilities:

Layout of Analog/Digital blocks, Mixer and Differential cell. This involved device and metal matching. Tools used Cadence VXL with Assura for LVS and Calibre for DRC, made any necessary corrections of errors.

Senior Mask Layout Designer

Confidential, Santa Clara, CA

Responsibilities:

Operated the Cadence Virtuoso tool to perform layout of TEST chip for Barracuda Project.
Run and correction of DRC/LVS/ERC using Hercules tool.
For the R&D group, layout of many Test Cells with the purpose of testing various design rule constraints.
Layout of Noise Gen, SIPO and Block level interconnect. Cadence tool with Hercules verification.
Engineering changes to the DOTHAN Project, Merced Project, Confidential ’s DLS Tool, Data Path layout.

Senior Mask Layout Designer

Confidential, Santa Clara, Ca

Responsibilities:

Mixed Signal Layout Analog Circuitry, Bandgaps, ADC’s and DAC’s
Cadence Virtuoso, DIVA/DRACULA verification tools, DRC/LVS/ERC checking and fixing any errors.

Senior Mask Layout Designer

Confidential, Santa Clara, CA

Responsibilities:

Batman project, layout of an E2 block used in the LMC6900 chip. Included memory interface cells and control logic. Device matching and balancing, data path layout. Planned and layout of various Logic Blocks to be used in chips (COP872, COP888GG, COP8SGR7) Implemented layout of I/O pad cells used in various chips.
DRC/LVS corrections of several Blocks that were shrunk from a 2µ to a 1µ process.