SUMMARY:

• Accomplished innovator & leader in electronic hardware and software design, development & manufacturing. A subject matter expert in design architecture, test & stress, with many published papers as well as chair of multiple conference sessions. Demonstrated excellence in driving technology teams, negotiating resolution to complex issues & engineering innovative hardware and software.
• Scrum and Agile methodologies, Strategic planning, product development, project management, negotiation, technical solutions, defect rate projection, cross - functional team leadership, individual and team development & mentorship.
• Hardware & software validation, simulation, emulation, fault grading, IC development & manufacturing, assembly & firmware level coding & testing, RTL, Verilog, ATPG/scan testing, BIST/LFSR test, functional test writing, logic test, cache test, IO test, IC reliability & RV (ESD, latch-up, electro-migration & hot electron) & hardware burn in.

TECHNICAL SKILLS:

Business Process: ISO 9000, agile, scrum process, lean process improvement, continuous business & process optimization, technical structured problem solving, production qualification methodology, intellectual property & patent filing, global export compliance, behavior based interviewing, laboratory & factory safety (ESD, electrical, chemical)

Communications: Coaching & mentoring, advanced presentation & public speaking skills, communications excellence, customer issue resolution

Debug, test & DFT development & design: Debug using Confidential ITP-XDP HW & SW access, scan design insertion & DRC, scan & ATPG generation, scan out implementation & development, advanced RTL design & development, advanced RTL simulation, IO DFT advanced design, Implementation of BIST & LBIST, circuit level simulation (Shark)

Circuit reliability: Advanced reliability statistics, advanced reliability failure & isolation, advanced transistor reliability, advanced metallization & interconnect reliability, advanced defect projection rate for integrated circuits

Circuit & IC design: High speed digital design principals, QuickPath & CSI interconnect design, Confidential architecture IA32, IA64 & SoC, advanced defect projection rate

Languages: Advanced x86 & x64 assembly, perl, python, C, pascal, csh, ksh, bash.

Software & OS: DOS, Windows, Mac OSX, Solaris, LINUX (OpenSuse, Suse, RedHat, Debian, Ubuntu, HPUX), MSDOS, openSSH, openVPN, vim, emacs, FTP/SFTP, VPN, VNC

Hardware: Confidential x86, Confidential x64, Confidential SoC, Sun, VAX, Apple, Alpha, Automated test equipment ( Trillium, Teradyne, Schlumberger & IMS), test equipment (Scopes/logic analyzers (HP & Tektronix)

PROFESSIONAL EXPERIENCE:

Product Development R&D Leader

Confidential

Responsibilities:

• Confidential driving innovation for product validation, test & stress methodologies across CPU architecture, design, development & reliability.
• Overhauled multiple aspects of stress methodologies, directing cross functional teams to create designs & methodologies to improve efficiency, including 3 patents pending. Led successful implementations which produced reduced complexity in hardware and software, in turn enabling savings of over $10M.
• Engineered fault tolerant stress signature methodologies for high volume manufacturing stresses, resulting in cost savings up to $2M per product.
• Devised initiatives that modeled stressing of a monolithic die with increased accuracy. Leading development & deployment efforts demonstrated savings of $1M per product.

Product Test Quality R&D Leader

Confidential

Responsibilities:

• Delivered complex coverage & defect modeling software tools to evaluate product quality early in the design life cycle. This solved systemic issues of under/over resourcing intensive test writing, enabling design groups to meet quality & time to market goals efficiently. Accurate assessments were delivered at 10% of the design life cycle instead of 60-75%, enabling 15-30% reduction in headcount.
• Analyzed & identified inefficiencies in fault grading & devised improved strategy & methods. Demonstrated proof of concept on a single product, which maintained quality but with a headcount reduction of 50%. Subsequently, directed the implementation of these methodologies & improvements across all CPU products.
• Addressed repeat customer quality excursions by creating a closed loop reporting system from customers to design engineering to ensure constant product quality improvement. Designed a systematic approach across all CPU products to ensure design issues found in the field were consistently corrected across all new designs. Leading the implementation of this reduced repeat customer excursions by 40%.

Platform validation engineer

Confidential

Responsibilities:

• Innovated & engineered cutting edge system emulation techniques to enable validation end to end, from circuit RTL to software GUI end point. Execution of a detailed validation caught 10’s of HW bugs & 100’s of software stack bugs before silicon and reducing post silicon debug time by 1/3.
• Devised firmware & software that would enable customers to observe internal signals, critical to their validation and restored debug capability, effectively reducing time to market and debug time by 2-3x.

Confidential, Hillsboro, OR

Product Development R&D lead

Responsibilities:

• Confidential driving innovation for product validation, test & stress methodologies across CPU architecture, design, development & reliability groups.

Confidential, Hillsboro, OR

Platform validation engineer

Responsibilities:

• Functional validation of 4th generation Confidential.
• Executed pre & post silicon validation of hardware and software stacks using RTL simulation & system emulation level.