Networking Engineering Resume Fremont, CA - Hire IT People

Education:

Masters in Computer Engineering
Course Work: Digital System Design with VHDL, Microprocessors, MOS Electronic Devices, VLSI Test Concepts, Cryptography and Network Security, Digital Integrated Circuits, Computer Network Architectures and Protocols, VLSI design for ASICs.
Thesis: Compact Implementations and Benchmarking of Two SHA-3 Finalists BLAKE and JH on FPGAs.
Bachelors in Electronics and Communication Engineering

Technical Skills:

Programming Languages : C, Assembly level programming, VHDL, Verilog, SystemVerilog, Perl,
Operating Systems : Windows XP/Vista/7, Mac OS, Linux.
Tools : Xilinx ISE, Altera Quartus II, Synplify Pro, ModelSim, MultiSim, Matlab, Cadence, Pspice, Microwind, Wireshark, TetraMax, Design Compiler, PrimeTime, Formality, IC Compiler.
Other Software's : Microsoft Office, Open Office, Microsoft Visio, LaTeX.
Miscellaneous : Excellent troubleshooting and debugging skills and also knowledge on Communication Protocols (TCP/IP, FTP)

Work Experience:

Graduate Research Student, Confidential, (GMU, VA) (Jan. 2010 - Present)

Designed and implemented compact architectures of Two SHA-3 Finalists BLAKE and JH, specially tailored for Spartan-3 FPGAs. The different implementations include block RAM version which uses embedded elements for storage and distributed RAM version which does not utilize any embedded elements.
Benchmarking of all the implementations using ATHENa (Bench-marking tool) for achieving maximum throughput/area ratio.
Other research interests include detailed study of architectural features of FPGA, Low-Area designing and True Random Number Generators.
Currently working on developing multiple architectures of BLAKE and JH for Spartan-6, Artix-7 and Virtex-6 FPGAs (Xilinx) along with Cyclone-5 and Startrix-5 (Altera).

Graduate Teaching Assistant, Confidential, (GMU, VA) (Aug. 2010 - May. 2011)

Courses: Basic Electronics Lab, Digital System Design, Microprocessors
Assist students in getting familiar with lab equipment, information about basic circuits and MSP430 debugging using IAR workbench.
Successfully monitored MSP430 project in which assembly codes are optimized and debugged on IAR workbench. The assembly codes are generated from Compiled C-codes.
Tutor students on weekly basis to help in ongoing course/lab work and assignments.

Projects Undertaken:

ASIC Design - ASIC Implementation of Compact BLAKE-32

Compact architecture of BLAKE-32 is optimized and implemented on ASICs using 90nm technology.
Implementation includes synthesis of the design, area optimization, timing analysis and Floor-planning using Synopsys ASIC tools like Design Vision, PrimeTime, IC Compiler.
Test patters are generated and functionality is verified using TetraMax and VCS.

Digital Design with VHDL - Implementations of Hash Algorithm

Designed and simulated both 32-bit & 64-bit variants of BLAKE for FPGAs.
Designed different architectures of both BLAKE-32 & BLAKE-64, which includes folded and unrolled architectures, optimized for better throughput/area ratio.
Simulations and assertion based verifications are performed at different levels to achieve post place route functionality using Xilinx Design Suite and Modelsim SE.

Microprocessors - Implementation of MSP430

Implemented computer architecture of MSP430, a 16-bit low-power micro controller using Verilog open source code.
Analyzing the computer architecture of MSP430 and implementing the same on Xilinx FPGAs.
Verifying the implementation by debugging with an assembly level program.

Cryptography and Network Security - Low Area Implementations of Cryptographic Hash Algorithm

Designed and implemented area constraint designs of BLAKE-32 on Spartan3 FPGA using VHDL language.
Developed low area architectures of BLAKE-32, which uses minimal logic resources and an embedded storage element. All the designs were simulated and optimized for better throughput/area ratio.
The designs are implemented with Xilinx tools using VHDL and functionality is verified at block and unit level using simulation tools like Modelsim and Isim.
Design of Full Adder using Microwind
Designed one bit full adder schematic and layout using Microwind and Post layout simulations using Pspice.

Simple On-Chip Communication with AHB Core

Design of two master and slave components to be integrated with the provided AHB Core.
Development of test suites with SystemVerilog, to verify the designed components along with the AHB Core using Modelsim SE tool.

Implementation of Serpent Cipher Algorithm

Designed and implemented Serpent Cipher Algorithm as a part of Final year project.
Responsible for implementation of key generation unit which produces 128/256-bit key for encryption and decryption.
VHDL language is used to develop the architecture of algorithm and implemented using Xilinx tools along with functional verification using Modelsim.

Publications:
J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270289, Dec, 2011.

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