Objective: Sr. Verification Engineer

Summary:

• Strong background in Digital Logic Design and Verification.
• Knowledge in Networking (PCI Express, Ethernet, TCP/IP), Computer Architecture and Memories.
• Debugging skills using Logic Analyzers and Oscilloscopes.
• Verilog, System Verilog, Assembly, PERL, VHDL, C, C++ programming.
• Familiarity with CAD/EDA tools for Design and Simulation.
• 4 Taped out ASIC Products on 65 and 45 Nanometer Technology for Flash memories.
• Experience in RTL, Post Synthesis (GATE) and Post APR simulation environment and debug.

Skills:

• H/W Description Language : Verilog, SystemVerilog, VHDL, Assembly
• EDA Tools : VCS (Synopsys), NCSIM (Cadence), HSIM, UltraSim.
  CAD Tools : Virtuoso(Cadence), Mentor Graphics Design Suite.
  Languages : PERL, C, C++.
• Tools & Packages : MATLAB, MS Office, Xilinx, Modelsim, Altera
• Platforms : Linux, Sun Solaris, Windows, Unix
  Debugging Tools : Novas Debussy, Verdi, DVE, SimVision (Cadence)

Experience:

Confidential, Sunnyvale, Ca, Design Verification Engineer May 2007 – Sep 2009

• Developed SystemVerilog timing checker to measure performance, flag hang scenarios, measure busy phases.
• Developed functional and algorithmic checkers to check funtionality of flash algorithm.
• Developed perl scripts and system verilog testbenches to add new features.
• Developed reference memory model with full MRS functionality.
• Developed detailed test plan for each user mode. Wrote 400+ tests to verify circuit correctness, full chip functionality, and coverage for each user mode scenario.
• Produced additional test scenarios for increasing coverage to 99%.
• Wrote exhaustive self checking test cases to test program and erase algorithm sequencing.
• Responsible for running full chip RTL, Gate and Post synthesis regressions and related test case debug. Regressions are run for any single change in RTL and assembly.
• Involved in development of OVM methodology, SystemVerilog random verification environment, write directed random templates and assertion based verification.
• Isolated many critical bugs in the design using the random templates and running regressions.
• Performed silicon debugging on the PISMO for different mask sets. Fixed all the PISMO related bugs written in C++. Debugged using logic analyzers. Reported all the software issues.
• Added a perl script to change a set of tests to run on PISMO software written in C++. Ensured that the silicon works.
• Assisted in verifying coverage and debugging the S29XS-T MirrorBit Eclipse Flash and S33MS-1 ORNAND2 Flash family of devices with successful tapeouts.

Confidential, Mountain View, Ca, Verification Engineer Sep 2005 – May 2007

• Performed testing of the Holly4 ASIC block and verified that the test cases matched the testbench behavior and the hardware requirements.
• Developed Perl scripts for generating a report and coverage.
• Developed test benches implemented in Verilog for multiple blocks in the Project.
• Developed and implemented the test plans used to conduct module level verification of various functions.

Confidential, Sunnyvale, Ca, Hardware Co-op Engineer Dec 2004 – Aug 2005

• Assisted in the debugging of problems found in the design of the Digital Interface Module developed in Verilog which is presently used in the Unified Test System for verification and test of the Unity chipset firmware.
• Assisted in the debugging of the DIM hardware using Logic Analyzers and Oscilloscopes.
• Conducted functional simulations using Altera’s Quartus II and ModelSim software simulator.
• Incorporated Altera Stratix FPGA, Texas Instruments Firewire chipset and SRAM into a prototype hardware design using Pads Logic schematic capture software.

Confidential, Hyderabad, India, Hardware Engineer July 2001 - Dec 2003

• Worked on the detail documentation of the test reports and test plans
• Assisted in the evaluation and procurement of parts for internal projects.
• Assisted in writing tests for the new features of FIFO models and Antenna models.
• Used Microsoft excel,Visio and Microsoft word for detail documentation.

Projects:

• TIVO FPGA CORE, Using Altera Maxplus and Verilog HDL, team designed and implemented a TIVO System, which allows users to pause, rewind, slow –motion.
• High Speed 64 bit CLA Adder, Using Cadence, designed and implemented an Adder, in TSMC 0.25 Micron Technology for 500Mhz speed. It was implemented in Dynamic logic using Carry look-ahead approach. Floor planning was done for the layouts. DRC and LVS were checked for the schematics and layouts.
• Pipeline MIPS Design, Using Altera Maxplus and Verilog HDL, team implemented a MIPS pipeline architecture using multiple cycle instructions, and datapath.
• FPGA Cache Controller: Using Synopsys and VHDL, I implemented a two-way set associate data cache comprising of a controller which communicates with the 486 processor, main memory, an address decoder with Hit/Miss logic and a static RAM.
• Researched 802.11 MAC, the WEP protocol and Kerberos authentication protocol.
• Implemented sorting algorithms using C++ classes and using C++ encapsulation, inheritance, polymorphism concepts in other class projects.

Achievements:

• Ranked 1st in 10th standard in county wide among around 5000 students in standard public exam.
• Awarded scholarship for ranking first in high school education.
• Award for the good quality of work at the current company.

Education:

M.S. degree in Electrical Engineering
B.S degree in Electronics and Communications Engineering