Circuit Design Engineer Resume

Objective: To obtain a position of analog IC design engineer.

Qualifications: Experience on memory chips in analog, mixed-signal, and digital IC design fields:

Analog design: Designed amplifiers, bandgaps, voltage regulator, charge pump, AtoD converter, comparator, PTAT current, bias & start-up circuitry, HV switches for Read and Write mode.
Mixed-signal design: Designed row/column decoders for memory chips. Verified test modes.
Digital design: Designed synch/asynchronous counters, shift registers, decoder, memory array for write protection.
Memory design: Experienced on FLASH, DRAM, and SRAM memory chips.

Technical Skills:

Circuit/Logic Simulations: Hspice, Hsim, ModelSim, Spectre, IBIS, Verilog/VHDL languages
Schematic/Layout tools: Cadence System Design, Mentor Graphics, L-Edit, Magic, and ViewLogic, check LVS, DRC, and RC extraction.
Computer skills: UNIX system, C++ programming, Linux, Microsoft Word, Excel, PowerPoint, Acrobat, FrameMaker
Master EE courses: Advanced Analog Integrated Circuit Design, Logic/Digital IC Design, Device Physics.

Confidential, Vermont (01/2008 – 03/2009) – Circuit Design Engineer
Participated in the analog design team to design DRAM memory chips.

Amplifiers: Designed several different high-speed operation amplifiers such as 2-stage op-amp, folded-cascode op-amp, telescope and wide-swing cascode op-amps.
Bandgaps: Designed an advantage high-speed and low-power voltage reference 0.8V. Also designed a voltage reference 1.24V for high power 1.8V/2.5V DRAM memory chips.
Regulators: Designed high speed voltage regulators for internal power supplies of memory chips.
Bias and start-up circuits: Designed bias and start-up circuits for bandgaps and amplifiers.
Power network: Built and tested the power network for memory chip.

Confidential., California (09/2000 – 05/2005) – Staff Design Engineer
Participated in the design team to design series of FLASH memory chips.

Charge pump: Designed a fast high-speed charge pump using a 4-bit A/D converter and triple-stage switched-capacitor circuitry for quickly boost the wordline path up to a high voltage during read operation mode.
Bandgap: Designed a high-speed voltage reference circuit.
Amplifiers: Developed and designed regular and cascode operation amplifiers.
Row/Column Decoders: Designed row-decoder ‘wordlines’ block and column-decoder’ bitlines’ block. Also responded on the READ critical path of flash memory chip.
Memory Array: Created a memory array for write protection’s block to shrink area of WP memory array to 60%.
HV Switches: Created fast high voltage switches for sending data to one bank in READ operation mode meanwhile sending another data to other banks in PROGRAM mode at the same time.
ATD: Designed Address Transition Detection ATD for memory chips using one-shot technique.
Familiar with test modes to check test functions for memory chip such as to test cells for Read/Program/Erase modes, HTDL mode, APD mode, leakage current test modes, etc….
Run IBIS model (Input/Output Buffer Information Specification) to provide a simple table-based buffer for devices in memory chips.

Confidential, California (06/1996–09/2000) – Design Engineer

Designed and developed a series of SRAM memory chips using CMOS technology
Designed Synchronous/Asynchronous counters, shift register, comparator, and decoder in CMOS technology.
Use JK and D flip-flops to design 2-, 3-, 4-, 5-, 12- synchronous counters and asynchronous ripple counters.
Designed Arithmetic Logic Unit ALU to be able to shift left/right, count up/down or restart.
Familiar with ESD protection, hypothesis, Schmitt trigger, etc….

Raytheon Semiconductor Corp. (05/1992-05/1996) – CAD Engineer

Library development: Analyzed, characterized and generate data for CMOS standard library.

Education: Major: Bachelor of Science in Electrical Engineering
Minor: Music