Objective:

• To obtain a position as Hardware /Electronic Design Engineer participating in the design and development of new products.

Tools/Skills:

• Verilog HDL, VHDL, ORCAD for schematic capture, Cadence Allegro for layout, Pspice, Concept HDL, Viewlogic , Pads Logic, FPGAs,CPLD, PCB, Modelsim/Verilog-XL for digital simulation, C programming. Synchronus serial communication, PCI bus architecture, High Speed Digital Design, Digital Logic Design, Analog Design, Strong analytical and problem solving skills.

Education:

Master of Science, Electrical Engineering

• Project: The Design of a High Speed Network Monitoring Card

Bachelor of Science, Electrical Engineering

Professional Experience:

Confidential
March 2010- July 2010
Mid-level Electrical Engineer

• Was involved in the design of one of their Network Cards (schematic capture using OrCAD , generating BOM’s ,gave my input for the layout engineer, troubleshooting the card) for space applications.
• Ran ATP on the card
• Working knowledge with copper 1000 Base_T and 1000 Base_CX interfaces.
• Protocol Knowledge of Gigabit Ethernet.
• Did some VHDL programming for their Xilinx FPGA’s

Confidential, Burbank, CA
September 2008- May 2009
Hardware Design Engineer

• Worked on the verification of the hardware design of the brake control unit of the Boeing 787 airliner. Designed a tester card to test the brake control unit.
• Worked in the Sustaining Engineering Department trying to find alternate parts or redesigning the whole board to accommodate the new part as a replacement.
• Analog circuit design (Op Amps, MOSFET ,ADC,DAC) ,used Pspice to simulate them.
• Digital circuit design used Modelsim to simulate them.
• ORCAD schematic capture.
• Used Altera Quartus II software design tool to write and compile Verilog/VHDL codes for CPLD/FPGAs.
• Supported board or unit during environmental testing such as temperature.
• Worked on Hybrids and did some troubleshooting on them.
• Worked closely with the Layout engineer to come up with a workable PCB board.Worked with manufacturing engineers and technicians to deliver functionable products.
• Familiar with EMI/EMC issues.Used troubleshooting tools such as Scope and Digital Meter for debugging digital and analog circuits

Confidential, Sunnyvale, CA
April 2008- August 2008
Hardware Design Engineer

• Worked on schematics using PADS Logic for high speed applications.
• ORCAD schematic capture.
• Programmed CPLDs/FPGA with Verilog codes using Xilinx tools (ISE 10.1)
• Troubleshot boards using Scope, Logic Analyzer, and Digital Meters.

Confidential, Sylmar, CA
June 2003-February 2008
Electronics Instructor

• Taught digital electronics, analog circuits, mathematics, and electronics communications.
• Taught one of the schematic capture tools they have such as Multisim.

Confidential, San Fernando, CA
April 2005-Sep 2005
Senior Hardware Design Engineer

• Low cost Microcontroller-based board design for embedded applications (Microchip,Atmel)
• Familiar with serial communication protocols (UART, SPI, RS-232, I2C). Board reverse engineering ability. Familiar with C codes and debugging for embedded applications.
• ORCAD schematic capture.
• Strong hardware debug and lab skills (Scope, Logic Analyzer).
• Did some analog circuit design.

Confidential, Santa Clara, CA
Dec 2000-Feb 2003
Hardware Design Engineer

• Designed and developed high speed PCB based on IBM750CXE embedded processor architecture utilizing Viewdraw (Viewlogic tool) for schematic capture, LVPECL, LVTTL signaling.
• ORCAD schematic capture.
• Working knowledge of embedded processors, system controllers, network processor IBM NPr 2.7, PHY and Link layer hardware and system components around it (OC3, OC12).
• Designed with EPLDs utilizing
• Altera design environment (Maxplus II). Captured designs with Verilog HDL, Graphic Editor.
• Working knowledge of high speed digital design, signal integrity issues, EMI, PCI bus architecture, SDRAM memory cycles, logic design.
• Experience in board layout utilizing Cadence tool (Allegro Layout). Hardware debug and lab skills (Logic Analyzer, Scope) and brought up prototypes in the lab and interfaced with software groups and vendors to deliver a completed product to manufacturing. Working knowledge of analog circuit designs and used Pspice to simulate them.

Confidential, San Jose, CA
Aug 1999-Dec 2000
Hardware Design Engineer

• Designed several high speed PCBs (Extender Boards) for mainframe tester.
• Utilized Concept HDL (Cadence Environment) for schematic capture.
• Knowledge of PCB layout utilizing Cadence tool (Allegro), Xilinx (Virtex) FPGA’s.
• Working knowledge of controlled impedance PCB design.
• Working knowledge of analog circuit design.
• Used Pspice to simulate analog circuitry.

References:

• Available upon request