Professional Summary:

• Over two years of professional experience as FPGA Research Engineer with strong expertise in designing, synthesizing and verifying complex FPGAs using VHDL, simulation tools, and in-lab debugging.
• High experience using Tektronix TLA 7012 Logic Analyzer, DPO70404B Digital Phosphor Oscilloscope and LPFK Protomat S62 PCB printer.
• Experience in prototyping ASIC and SoC designs on FPGA-based platforms.
• Implementing complex DSP logic for Xilinx FPGA systems using VHDL.
• RTL and Board level digital design using Xilinx FPGAs.
• Quick Script development using Perl, shell and C/C++ on Unix/Windows environment.
• High experience with FPGA-embedded processors (MicroBlaze, NiosII, PicoBlaze).
• Research in Pico Computing M-503 Virtex 6 FPGA modules using standard DDR2,3 and 8x, 16x PCI-e interface.
• Knowledge on Processors, TCP/IP networking, image processing/DSP algorithms on FPGAs.
• Experience developing Projects using VIO, ICON cores on Chipscope Pro Analyzer for .
• Hands on Experience using Mixed Signal Oscilloscope for Virtex 5/Spartan 3E.

Technical Skills:

Languages: RTL in VHDL, Perl, TCL, Embedded C/C++, OOPS IC Design: Mentor Graph IC Station Layout/Schematic Development: Xilinx ISE 13.2, Altera Quartus 11.0, TI Code composer studio v4 Simulation: ModelSim, LTSPICE, HSPICE (Complex Analog/Mixed signal simulation) FPGAs: Xilinx (Spartan 3/3E and Virtex II pro/5/6), Altera (Stratix IV and Cyclone IV) PCB Design: Cadence Orcad/Allegro, Altium Designer

Education: MS in Electrical Engineering

Graduate Thesis:

A Study of Multiprocessor System using PicoBlaze 8-bit Microcontroller Implemented on FPGAs: An array of soft processor cores using the Xilinx PicoBlaze embedded 8-bit microcontroller was implemented on Spartan 3E and Virtex 5 FPGA development boards. Mailbox and Shared memory Interprocessor communication schemes are evaluated. Using Mailbox interprocessor communication, an array of 14 PicoBlaze processors was produced and a simple FIR filter was implemented. Using Shared memory interprocessor communication, a round-robin arbiter with four PicoBlaze processors sharing a common memory was implemented. Tektronix TLA 7012 Logic Analyzer and DPO 70404B Digital Phosphor Oscilloscope are used to measure delay statistics. Test bench was created and simulated in Mentor Graphics ModelSim to compare the results obtained in Logic Analyzer. Background research includes study of Altera NiosII, Xilinx MicroBlaze, Sun OpenSPARC embedded processors. Coding was done in VHDL. Xilinx ISE Design Suite 13.1, Xilinx Core Generator, Floor Plan Area, Model sim, FPGA editor, and Chipscope Pro are the tools used in the research. Spartan 3E, Virtex 5, Virtex 6 and Digilent Basys2 FPGA development boards are used.

Professional Experience:

Confidential, Tyler TX (Aug' 09 - Aug' 11) FPGA Research Engineer

Overview of Research Projects: 8-bit PicoBlaze Embedded Soft-core Processor for Spartan and Virtex FPGAs in VHDL:

Responsibilities: Projects that make use of PicoBlaze embedded soft core on Virtex-6 and Spartan-3E are built for class course work and lab demonstrations. Those include the following. 1.Simple Addition, Multiplication on soft-processor was performed and result was displayed on LCDs of FPGA boards. 2. Digital to Analog Converter project was performed in VHDL using the PicoBlaze Soft-processor that samples the data at 8kHz. Analog Outputs are verified on Tektronix Mixed signal Oscilloscope. 3. 'Counting numbers' Project using multiple PicoBlazes that demonstrates the multicore processing effect.

DDR3 Interface using Xilinx Virtex-6 FPGA: Responsibilities: Generated a custom MIG (Memory Interface Generator) core in Xilinx Core Generator to interface with the DDR3 component on Virtex-6. Also, created ILA and VIO cores in Xilinx ISE 13.2. Using VIO console of Chipscope Pro Analyzer, data patterns were observed and verified. This Research project can be enhanced to develop FPGA projects that use DDR3 units.

Data Read/Write Using ML605 Virtex-6 PCI-e x8 Interface: Responsibilities: Research in verification of PCI-e interface with Virtex-6 ML605 board. At first, PCI-e core was generated in Xilinx Core Generator with customized memory and data paths. Then, Xilinx ISE 13.2 was used to synthesize, implement and program the FPGA. Platform Flash was programmed with PCI-e design and FPGA was inserted into the 8x PCI-e slot. Finally, using PCI-Tree Bus viewer, data registers and the address locations were accessed. Read/Write operations (data was loaded, copied and retrieved) using PCI-e interface was performed. This project overviews the use of PCI-e interface and outlines data communication between FPGA and PC.

FIR Filter on Virtex-6 ML605 Using Multiply Accumulate (MAC) and Distributed Arithmetic (DA) Architectures: Responsibilities: At first, FIR Filter compiler was Instantiated using Core Generator. MAC was taken and a single rate FIR is implemented using single MAC engine block. Using Distributed Arithmetic (DA) FIR Filter, Serial DA mode Filter was designed using shift registers. Statistics of both architectures are compared and plotted.

PCI-e and DDR3 Interface of Pico Computing M-503 Virtex 6 FPGA Modules: Responsibilities: Using M-503 Pico computing Virtex-6 module, sample projects are run and verified. Pico-Bus Counter project is configured and verified using PCI-e interface. This project counts, read/writes the data into Pico Card . Using two independent banks of DDR3 SODIMM interface with Virtex-6 LX240T FPGA module, image and signal processing projects are theoretically verified and outlined for future research and development.

Digilent Basys2 Spartan 3E Projects: Responsibilities: Stopwatch, Timer, Traffic lights, 4-Bit counter, Scrolling data on Seven segment display- lab projects are coded in VHDL and documented. Using Xilinx ISE 12.1, course projects are developed meeting deadlines.