ASIC design/verification engineer Resume Irvine, CA - Hire IT People

OBJECTIVE

Looking for a challenging position as an ASIC design/verification engineer where I can learn and grow.

SUMMARY OF CREDENTIAL

Comprehensive knowledge of the methodologies and applications of verification tools
In-depth knowledge in digital VLSI circuit and system design
Strong Verilog, C++, JAVA skills
Knowledge of System Verilog, PERL
Strong background in high speed analog/mixed signal circuit design
Knowledge of computer and mobile communication system

PROFESSIONAL EXPERIENCE & PROJECTS

Confidential, (Verilog, Modelsim, Synopsys Design Compiler & PrimeTime, Cadence Conformal & SOC Encounter)

Memory Controller - Design a DDR2 memory controller block to communicate with DDR2 memory through the SSTL interface and supports multiple functions. DDR2 Initialization engine and an output ring buffer are also implemented. Pre and post synthesis verification are performed in both functional and timing aspects. Synopsys tools are used for synthesis and timing analysis. Cadence tools are used for Logic Equivalence Checking and Place/Route Automation.
Traffic Light Controller - Design and verify a traffic light system that can change states automatically with predefined intervals.
Computer System Design - CU and DPU design for multi-clock-cycle and pipelined CPU; Computer arithmetic and memory hierarchies. Design blocks "Min-Max Finder", "4-bit ALU with SLT", "Bubble Sort", "Multi-cycle CPU", "Pipelined CPU" using Verilog.
Other Projects - "Sequence Detector", "4-input LRU priority encoder, Parallel in Serial Out(PISO)", "Serial in Parallel Out(SIPO)"

Confidential, (Cadence, Spectre Compiler, Schematic, Layout, LVS)

Arbiter for system on chip packet routing - RTL design, Layout and verification of an Arbiter which takes in multiple inputs, generates clocked group of outputs according to LRU priority.
Other Projects - "16-bit absolute difference circuit", "2K Bit SRAM", "8-bit Baugh-Wooley Multiplier Design", "Ripple Carry Adder", "Carry Select Adder", "Full Adder" .

Confidential, (SPICE tools)

RF filters Design Projects: "Delay Equalizer" - Design a Low-pass delay equalizer that delivers maximally flat delay based on the fifth-order Bessel-Thomson architecture with specified design constraints.

WORK HISTORY

Confidential, LLC - Application Engineer, May 2011 - Aug 2011

RF packaging, power electronic packaging, optoelectronic packaging, semiconductor lasers, PWB manufacture and silicon die assembly

Confidential - Research Assistant, Jan 2009 - May 2010

RFID antenna on metallic surface: Antenna Minimization; impedance modification; testing and verification.
Antenna with isotropic radiation pattern
Design and fabrication of dual-frequency antenna for cellular phone
Antenna and Wireless Communication Testing: TIS and TRP measurements for mobile terminals (cell phones, PDAs, laptops, etc.) and base station antennas (CDMA, UMTS, WiFi, WiMAX, RFID) using the SG 128 multi-probe antenna test system and radio communication instruments

EDUCATIONAL QUALIFICATIONS

MS in Electrical Engineering VLSI
Bachelor of Electronic Engineering

OTHER SKILLS