SUMMARY

• Experience in PCB circuit boards (OrCAD/Allegro v.17.2) include FPGA v.6 and Zynq 7000 for Video/Imaging and high speed transceivers with ISE/Vivado Navigators (RTL, AXI XDC Constraints, Place and Route to Bit Stream generation), Vxworks, DSP TI and ADI high speed TxRx, PCI/DDR, En/decoders, ADC/DAC in C/T/FDMA, 3/4G, CPRI WiMAX/GSM/LTE, and etc.
• Performed LTE/3G4G/TxRx include PLL, OSC, LNA/PA, n - QAM/EVM, Mixers, Mux/Demux, S-para (S11,..,S22), BER, EVM, SNR/SINAD, NF, Sensitivity, 1dB, OIP3/5, EMI and etc.
• Experience in Cadence OrCAD/SPICE/Virtuoso, and SoC verifications and UVM/OVM testbench environment (assertion, sequence, scoreboard, and etc) and tape out.
• Developed code and drivers in Matlab, Pythons, C/C++ VB, NI Labview/Teststand/CVI with NI chassis/modules (CTRL, A/DIO, DAQ, PXI, and etc.) and Agilent such as VSA, Gen and Spectrum 4440E, VNA 5062A for Digital/RF LTE/Microwave include GPIO, RS232, RS485, LAN IP, IPV6/V4, 802.3 and 802.11 (SAP/TCP/UDP L1-4 protocols) and more.
• Experience in management people in design/test projects, labs, manufacturing floor, customers, and all other issues solving problems.

PROFESSIONAL EXPERIENCE

Confidential, Fremont, CA

Sr. Electrical Engineer

Responsibilities:

• Designed and integrated EFEM wafer handlers. Selected new part replacement and solved customers’ issues.
• Supported and upgraded manufacturing products and modified AutoCAD 2020 electrical/mechanical drawings and modified BOM in Expandable.

Confidential, Fremont, CA

Staff Design Engineer 

Responsibilities:

• Designed schematic capture and layout using Cadence PCB design tools (17.2) and troubleshoot system include PID for Robo/motor controllers, D/AIO, and other related.
• Created cable drawing and assembly for systems such as Hydrillis tool built include RF Matching/Power Gen Chambers (2Mhz, 13.56Mhz), B&R PLC Ethercat (Controllers, AIO, DIO modules) for controlling robots, pneu, pumps, and other devices, block and cable assembly drawings
• Integrated NPI Plasma group in the design and problems solving.
• Experience in system test/troubleshoot include Robots and RF generators ignite Plasma chambers.

Confidential, Peachtree, GA

Software/Hardware Verification Engineer

Responsibilities:

• Verified RTL code and created coding SV/UVM Verilog testcase and testbench environment (assertions, sequence, mail, monitor, score board, checkers, generators and other interfaces like as AMBA, AXI and others)
• Developed Teststand/Labview for integrating Self-driving and Audio automation using Agilent/Keysight U8903B model, Confidential wireless test set, AVR function generator, NI modules (AIO, PXI, DIO, DAQ, CANBus) and etc.

Confidential, San Jose, CA

R&D Engineer in Research

Responsibilities:

• Developed C++/Matlab/ Labview code for Plasma/Ion Beam wafer deposition systems and Alpha Beta ion beam systems include CAN/cDAQ, IMAQ, Vxworks, Bechkhoff PLC Twincat for Pneu, Pump, Robot controllers and RF HP Amp.
• Developed firmware for Robo controller (Vxworks, ISE and Vivado, DSP TI studio) and Python for Newport XPS,300 series, Zaber motorized stages and Robotics controller boards PID and others.
• Supported scientists, PhD, and supported intern students for complete projects in R&D labs such as Wafer measuring in RF using Signal Gen, Spectrum, Power meter, VNA and others.
• Knowledge in Machine Computing include Deep Learning Algorithm and Neural Net.
• Designed PCB Schematic capture/Layout/Fab using Cadence 16.2.

Confidential, CA

RF Engineer

Responsibilities:

• Managed and supported Satellite Space install/debug/test verification for system tests before lauching.
• Performance Design/Test RF modules include H/C Temperature/Vibration/Pressure in RF/Microwave using Signal Gen, VNA E5062A, and more.

Confidential, Santa Clara, CA

FPGA Engineer

Responsibilities:

• Verified a FPGA Zynq 7000 model for Video/Imaging using ISE/Vivado tool, Matlab Simulations and Bit map download into FPGA Zynq 7(RTL, AXI interconnect, Place, Route to Bit stream), DSP/WiMAX CPRI UMTS/BB, ADC/DAC, and other FPGA Bus protocols for Satellite Communications Systems.
• Developed UVM testcase and testbench environment (assertions, sequence, mail, monitor, score board, checkers, generators and other interfaces like as AMBA,AXI and others)
• Tested and debugged board using NI cDAQ 9178, Signal Gen, VNA E5062A and more.
• Coordinated and developed Python,C++,WindowCVI/ Labview code with other engineering team.

Confidential, Lowell, MA

Verification Engineer

Responsibilities:

• Verified chipset of SoC for tape out and coding SV/UVM Verilog testcase and testbench environment (assertions, sequence, mail, monitor, score board, checkers, generators and other interfaces like as AMBA, AXI and others)
• Worked on Xilinx FPGA v.6, DSP/WiMAX CPRI, ADC/DAC, and other FPGA Bus protocols (802.3).
• Tested and debugged board proto and chipset on pilot boards include WiMAX/Wifi/GSM, Signal Gen, VNA E5062A for measurements such as n-QAM/EVM, and more.

Confidential, Campbell, CA

Staff Engineer and Lab Supervisor/Manager

Responsibilities:

• Verified Silicon chipset on Wimax, UMTS AXIS BTS and RF board projects on both Baseband/Digital IF/RF sections using Cadence Suite, Xilinx ISE Navigattor EDK/SDK, IFFT/FFT, PSK/n-QAM/EVM, and DSP/WiMAX CPRI, TI CCS C6000 series with fixed floating simulations, C algorithms for Real time DSP, Xilinx FPGA VHDL, Matlab & Simulink, Agilent VSA 896xx series capture tool.
• Developed UVM testcase and testbench environment (assertions, sequence, mail, monitor, score board, checkers, generators and other interfaces like as AMBA,AXI and others)
• Created bit stream and implemented ML40x proto boards using 802.3, Ethernet/IO, PCIe, procedures, demo to customers, lab budgets, and parts/instrument orders.
• Familiar with Signal Gen, PXI, VNA and so on.

Confidential, Morga Hill, CA

HW Development Engineer

Responsibilities:

• Worked on schematics using Mentor tool and characterized RF Microwave design such as LNA, PA using MMIC modules/devices, and SONET E1/E3 Networking.
• Performed in developing, designing and supporting floor production on ATE using Visual Basic and Labview/fixture/closure.

Confidential, Santa Clara, CA

Technical Staff Engineer

Responsibilities:

• Designed custom boards using Cadence 9.2 Schematic Capture/Layout for customers such as Cisco, WirelessLAN, Confidential and etc.
• Designed PCB test fixture and built-in automations rack for customers.
• Worked on-site customers for developing and implementing code (Perl, Python,C++, Labview/CVI) to those companies and managed our projects and engineering team.
• Supported production lines including tests, debugs, and customers.
• Familiar with RF/Digital Networking using SigGen, Lightpoint, NPR measurement instruments and more.
• Developed Labview code for TxRx and PA modules using VNA E5062A (S-parameter and Smith chart), fixture/closure, power supplies and others.
• Coordinated with other team to understand the specification for developing script file.