PROFESSIONAL EXPERIENCE

Confidential, Dallas, TX

Digital Design Engineer

Responsibilities:

• Documented and designed Verilog RTL with DFT components for digital VCO calibration and programmable clock dividers for high - speed mixed-signal chips running up to 1.2 GHz.
• Synthesized design with DFT SCAN chains using Synopsys DC and Cadence RC with SDC timing constraints using TI ASIC libraries. Fixed all SCAN problems in RTL for high SCAN coverage.
• Created an unique and successful EDA synthesis methodology to increase digital netlist clock speeds from MHz to GHz for greater design performance, with smooth translation through the final backend layout process.
• High-quality netlist hand-off to the back-end team for very efficient, low-human-effort place and route layout.
• Ran Spyglass for RTL linting and created an ASIC Checker utility for Synopsys design examination.
• Verified RTL and gate-level netlists using Cadence NCSim and back-annotated SDF with created Verilog self-checking testbenches.
• Supported the back-end team and performed post-layout static timing analysis with SDC and SDF (min, typ, max) in PrimeTime.
• Oversaw layout and clock tree analysis.
• Netlist hand-off to client and provided customer support for the design use.
• Interfaced with analog engineers to develop mixed-signal RFICs.
• Designed digital ADC, filter, mixer, and angle of arrival components for a low band digital filter receiver.
• Created Verilog RTL for Xilinx Virtex 6 FPGA implementation.
• Utilized Xilinx CoreGen for DDS (Direct Digital Synthesizers) for sine/cosine NCO (numerically controlled oscillator) Verilog code generation.
• Hand instantiated Xilinx Virtex-6 FPGA DSP48E1 core into Verilog RTL modules for high speed (approaching 600 MHz) mathematical functions.
• Developed Verilog testbenches for each RTL module along with design specification documentation.
• Used QuestaSim and Matlab for verification simulations.
• Ran timing-driven place and route in Xilinx ISE.
• Digital and analog design/verification engineering with focus on chip level design.
• Managed electrical engineering laboratory work.
• Produced weekly technical presentation material (content creation) for engineering instruction.

Confidential, Richardson, TX

Digital Design Engineer

Responsibilities:

• Developed the ASIC/FPGA tool flow for Confidential 's Wireless Systems Lab HW Digital Engineering organization for low-power handset and base station projects, using Synopsys Design Compiler-Ultra, DFT-Compiler, Power-Compiler, PrimeTime, Xilinx, and Mentor Graphics’ FormalPro for 65nm and 90nm technology on LINUX/UNIX platform.
• Designed Verilog RTL for DSP filters and mathematical blocks for ASIC/FPGA devices for consumer cell phones.
• Generated synthesis, power, DFT for SCAN, and static timing analysis SDC constraints for individual Verilog RTL blocks and for the top-level core which were used by DC, DFT-C, Power-C, and PT.
• Performed low-power synthesis and gate-level power analysis with VCD and SAIF using Power-Compiler.
• Created an ASIC checker utility for fast feedback to designers and technical management on the status of Synopsys synthesized netlists so that the design team can make more informed decisions about their RTL architecture early in the design process and for documentation.
• Constructed Verilog testbenches for individual RTL modules and ran simulation in ModelSim.
• Front-end team “Point-Man” for back-end interface with the ASIC vendor.
• Mentored and guided junior ASIC/FPGA engineers on front-end design tasks and back-end interface duties.

Confidential, TX

Manager/Lead Design Services Engineer

Responsibilities:

• Manager and team lead of a design group that supported multiple on-site and off-site customers with their ASIC, FPGA, and SoC IP core integration design projects.
• Technical pre-sales interface and post-sales support of company customers.
• VHDL and Verilog RTL design, synthesis, testbench creation, simulation, static timing analysis, and backend place & route for consumer products.
• Video MPEG-2 FPGA design project work.
• Created and led client presentations and demonstrations in small and large group settings.
• Technical pre-sales interface and post-sales support of company customers.
• Created and led client presentations and demonstrations in small and large group settings.
• Managed project schedule, resources, and issues.

Confidential, TX

Staff Design Engineer

Responsibilities:

• Lead designer on the UTOPIA-2(IP01) project. Verilog RTL design on 4 projects.
• RTL synthesis to ASIC and FPGA implementations using Synopsys Design Compiler.
• DFT SCAN insertion during synthesis using Synopsys Design Compiler and Test Compiler.
• Ran ATPG using Synopsys TetraMax to create SCAN vectors for high SCAN coverage.
• Created a Synopsys ASIC checker to find post-synthesis design problems early in the flow.
• Verilog self-checking testbench creation for verification effort and automated regression process.
• Core integration for SoC at the RTL level, verification at RTL and SoC netlist levels, and oversaw backend effort.
• RTL, SureCov (code-coverage), and gate-level simulations with worst, typical, and best case SDF using Verilog-XL and NC-Verilog simulators and Signalscan for waveform viewing.
• Performed SureCov analysis to examine entire verification test suite for uncovered portions of the design, with the goal of 100% block coverage.
• Placed and routed designs in Xilinx FPGAs for design emulation before ASIC silicon.
• FPGA to ASIC migration on 3 telecom projects.
• Created layout floorplans for various designs.
• Interfaced with layout team by providing post-synthesis netlist, timing constraints for timing-driven place and route, clock tree generation constraints, design floorplan, and critical path information.
• Ran static timing analysis with SDF (worst, typical, and best) using Synopsys PrimeTime.
• Performed post-layout synthesis reoptimization using Synopsys Floorplan Manager with the post-route PDEF, SDF, and "set load" capacitance/resistance information.
• Ran formal verification using Synopsys Formality.
• Lab tested ASIC and FPGA devices using various lab test equipment.
• UTOPIA-2 design was a first-pass silicon success.
• Instructed junior designers concerning ASIC and FPGA design engineering tasks.

Confidential, TX

ASIC Design Engineer

Responsibilities:

• Implementation team lead for PCI digital devices.
• Performed silicon debug IDS10K failure/root cause analysis on ASIC chips.
• Executed Synopsys Floorplan Manager reoptimization using PDEF, SDF, and net capacitance information.
• Performed TI cost analysis on a series of new ASICs.
• Wrote tool scripts for Synopsys synthesis.
• Performed RTL and post-layout SDF simulations using ModelSim, Verilog-XL, and Signalscan.
• Created static timing analysis scripts for Synopsys PrimeTime.
• Lead ASIC designer for the bus interface chip on the HSIS project.
• Wrote VHDL RTL for the ASIC design.
• Synthesized the RTL using Synopsys Design Compiler.
• Performed RTL and gate-level simulations using ViewSim.
• Inserted SCAN using Synopsys Test Compiler.
• Responsible for support on 5 ATM ASICs.
• Synthesized VHDL RTL using Synopsys Design Compiler.
• Inserted DFT SCAN and ran ATPG using Synopsys Test Compiler.
• Fixed timing violations in Compass layout, Synopsys synthesis, and VHDL RTL.
• MBIST strategies evaluation for the ASIC RAM components.
• Created various Synopsys utilities and scripting for more efficient ASIC design flow, including an ASIC design checker and an in-place reoptimization tool.
• Responsible for verification of the Motorola ATMC ASIC.
• Created VDHL tests for mixed VHDL, Verilog, and LMC model simulations using ViewLogic's Fusion simulator.
• ATMC ASIC was a first-pass silicon success.
• Designed 4 Xilinx and 1Altera FPGAs in VHDL for datapath control for the OC-3 SONET platform.
• Used Synopsys Design Compiler for synthesis.
• Placed and routed the designs using Xilinx and Altera backend tools.
• Performed RTL and back-annotated gate-level simulations using Mentor Quick-HDL.
• Ran static timing analysis using Synopsys DesignTime and Xilinx tools.
• Lab tested all devices during integration on the platform.
• Applied and received a patent for this design (patent #6,044,088).
• Design Engineer on the Next Generation Signaling Server project:
• Developed VHDL testbench for RTL simulations of a PCI device.
• Created PCI protocol procedures in VHDL for reuse on multiple designs.
• Synthesized VHDL using Synopsys Design Compiler.
• Designed 4 Xilinx FPGAs in VHDL RTL to perform datapath control.
• Placed and routed the designs using Xilinx backend tools.
• Performed static timing analysis using Synopsys DesignTime and Xilinx tools.

Confidential, TX

Digital Design Engineer

Responsibilities:

• Responsible for 3 LSI Logic ASICs.
• Created VHDL RTL to implement over 30 DSP, ALU, and I/O functions.
• Simulated RTL using Vantage VHDL simulator.
• Synthesized ASICs using Synopsys Design Compiler.
• Verified gate-level functionality by accelerated simulations using IKOS and stimulus/result vectors generated from the C-language system-level testbench.
• All 3 ASICs were first-pass silicon successes.
• Obtained D.O.D. secret clearance in early 1992.
• Responsible for 2 TI ASICs.
• Synthesized ASICs using Synopsys Design Compiler.
• Performed RTL and gate-level simulations using ModelSim and ZYCAD.
• Inserted CBIST SCAN throughout the chips.
• Ran static timing analysis using TI internal tools.
• Designed VHDL behavioral models of various chips for board-level simulations.