Graduate Trainee Design Resume

SUMMARY

Master of Electrical and Computer Engineering wif core competence in ASIC/SoC Design and Verification. Experience in VIP development and Validation. Seeking position as Design Verification Engineer.

PROFESSIONAL EXPERIENCE

Graduate Trainee Design

Confidential

Responsibilities:

VIP component development for AXI 3.0 protocol wif support for various features. As part of dis project developed BFM, Generator, Monitor, and Coverage Models. Developed scenarios targeting validating teh features.
Developed teh testplans and coded teh VIP components and validated AXI VIP using slave model.
Developed a testbench that generated all types of Ethernet packets which included listing down features and scenarios(Constrained random verification). Developed a reference model for self - checking teh design behavior.
Implemented teh functional coverage for teh switch protocol and analyzed teh coverage results.017
Built layered testbench architecture using constrained random stimulus for teh ALU. (Transaction Level Modelling)
Implemented command monitor, result monitor, command transaction, result transaction, driver, interface, sequences, scoreboard, coverage classes for constrained random verification using UVM.
Teh Testbench delivered 100% functional coverage, which checked that all teh operations worked properly.

APB Interface protocol

Confidential

Responsibilities:

Implemented UVM Verification components like APB Transaction Item, APB Master Driver, APB Master Sequencer, APB Monitor, APB Environment, APB Test, APB Sequences.
Compiled, Simulated and debugged teh test to analyse teh transactions driven by teh driver and check if same transactions are observed by teh monitor component according to teh specifications.
Succeeded in implementing teh standard cell based ASIC Design flow for Carry Ripple Adder, Carry Lookahead Adder, Carry Save and Carry Select Adder CPU Designs.
Summarized teh performance comparison of all teh adder CPU design.
Designed module of processor such as Register File, Data and Instruction Memory and Control Unit.
Integrated all these modules to form Single Cycle MIPS Processor and analysed teh results of simulation.
Implemented Loop Unrolling and Cache configuration technique for sorting algorithms by 16%(System-level)
Implemented Clock gating technique and reduced teh power consumption by 25%. (RTL -Level)

TECHNICAL SKILLS

Programming Languages: Verilog, System Verilog, C, C++ Scripting Languages PERL

Verification: UVM, System Verilog Assertion (SVA), Functional Coverage, Constrained Random Verification, Debug

EDA TOOLS: QuestaSim, Synopsys Design Compiler, Encounter, Cadence Virtuoso, HSPICE, Formality ESP, ModelSim, CAD Tools, GIT, UNIX, Linux and Windows Protocols AMBA (APB, AXI)

Others: RTL Design, RTL Synthesis, netlist to GDSII, Static Timing Analysis, Computer Architecture, SoC Verification

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