PROFESSIONAL EXPERIENCE

RFIC/Analog/Mixed - Signal Design Consultant

Confidential

Responsibilities:

• Redesign, debug, and verify VCO, PLL and Phase Interpolator for the next generation of high speed SERDES using for Cloud Server
• Architected & designed Low power Low ON resistance Power switches for power management for portable electronics. The switches offer very low ON-state quiescient current and OFF-state leakage current.
• Designed Low power Bandgap reference, Regulator, currrent reference, reversed current sensor, opamp, comparator, oscillator, automatic supply selection for power saving.
• Designed, simulated, laid-out RF Front-End circuits for mobile phone Receiver
• Wrote verilogAMS models for LNA, Mixer, LPF, ADC, PLL, etc… for data Transceiver and Power Management for USB Power Delivery. Built testbenches, ran simulation to verify analog/mixed-signal designs in transistor-level to verilogAMS models.
• Built top-level testbenches and run RX & TX system verifications
• Floorplanned and Laid-out programmable RF peak detector with DC offset cancellation for 2G/5G mobile phone. The design contains RF Buffer, AGC, DAC, VCM and Bias circuit
• Laid-out 10GHz, 5GHz LO Dividers and Drivers, and regulator
• Designed and laid-out RF amplitude detector with 2 bit RF Gain settings for silicon TV Tuner covered from 40MHz to 1GHz
• Designed and laid-out cyclic ADC, Bandgap, regulators, voltage and current reference circuits.
• Designed RF/Analog circuits such as LNA, Mixers, 6GHz LO I/Q Generator, Low Noise LDO for VCO, regulators, Bandgap, etc… for Wide-Band Wireless RF transceiver operating from 300MHz to 3GHz. This is a single chip solution targeting for mobile broadband 3G & 4G/LTE and white space
• Floorplanned entire chip including RX, TX, PLL
• Designed on-chip Power Management for entire LTE chip
• Ran system level verification for the GSM/UMTS/EDGE/WCDMA/TDSCDMA transceiver using Cadence AMS-UltraSim mixed signal simulator for system startup and calibration such as reference calibration, DC Offset cancellation, etc…
• Designed automatic calibration circuit using 10-bit Cyclic ADC for 4G mobile phone

Principal Design & Application Engineer

Confidential, San Jose CA

Responsibilities:

• Provided Methodology and Design Services to Cadence customers
• Designed and simulated RF Front End blocks: LNA and Mixer
• Ran Substrate Noise Analysis on LNA and other circuits
• Ran Surface Noise Coupling Analysis on LNA and for Wireless Receiver
• Designed, Simulated and laid-out DigRF LVDS Receiver and Driver operating in both 1.8V and 1.2V supplies. The data rate is from 5 to 400 Mbps. The transceiver contained 0.5V and 1.2V Bandgap references, PTAT currents, 1.2V and 1.8V regulators, Differential to Single-Ended Amplifier, Bias currents, Level Shifter, Differential Analog Output Driver, Digital Pre-Driver, Op amps, Input and Output Buffers with ESD circuits
• Wrote and verified VerilogAMS behavioral models for the WLAN 802.11b Transceiver and Frac-N PLL and then compared with the transistor-level design.
• Ran Receiver system level simulation in transistor-level and verilogAMS and compared the results
• Ran loop back system level simulation with random input patterns injected into Transmitter inputs and compared the Receiver outputs to the input patterns.
• Helped customers do design verification from transistor level up to system level simulations
• Worked with customer to establish standards in Full Chip Mixed Signal simulation
• Ran Jitter and Phase Noise analysis on VCO and on closed loop DLL
• Visited customer for pre-sales VCAD service and technical discovery
• Provided technical support and mentor to RFIC team members especially in RF/Analog/Mixed Signal design knowledge area
• Provided inputs and supports toward RF and PLL kits during definition, development, and deployment phases

Sr. Analog/Mixed Signal IC Design Engineer

Confidential, San Jose CA

Responsibilities:

• Acted as Technical Lead in Analog/Mixed Signal design team. Managed engineers, oversaw design specifications and aligned to internal and external customer requirements
• Designed low power Active RFID transceiver in 0.18um CMOS process in Mentor Graphics with low power dissipation and less external components for cost effective
• Co-designed GFSK Bluetooth transceiver Architecture and Specification
• Designed Switch Capacitor Bandgap circuit, Regulators, and Crystal Oscillator
• Designed Band Pass Filter, Limiter/RSSI, GFSK demodulator for Low IF receiver
• Designed low power 8 bit Switch Capacitor ADC
• Designed Fractional-N PLL which includes VCO with coarse tune and fine tune capability, Phase Frequency Detector, Charge Pump and Prescaler/Divider
• Floorplanned layout integration for Analog/RF chip
• Debugged and verified Delta Sigma Fractional-N PLL design provided by Kaben Research and proposed design improvements to the Charge Pump circuit.
• Inspected, and verified sub-blocks of the CDMA receiver for multi mode multi band cellular phone, ie, LNA, up/down Mixers, VGA, RF buffer, …
• Re-designed Bandgap circuits for RF Front-end

Principal IC Design Engineer

Confidential, Sunnyvale CA

Responsibilities:

• Designed Ultra Low Power Hercules Analog IC, Xena Digital IC, and High Voltage Thor ICs in which this chip set has been used in the market for multiple Bradycardia and Tachycardia products.
• Designed extremely low power management circuit and system for pacemaker and defibrillator ICs: DC-DC switching regulator, LDOs, switch-cap voltage & current references, low battery detectors, amplifiers, level shifters, etc…
• Re-designed a very low power 32KHz XTAL oscillator. Designed a ring oscillator with 6 bit frequency selectable capability from 0.5M to 10MHz. Designed programmable VCO and Fuel Gauge circuits to give the battery life status.
• Re-designed Activity Sensor to detect the movement of patient who has defibrillator or pacemaker implanted.
• Analyzed and simulated Switch Capacitor Filter circuits, and ADC for Defibrillator
• Debugged, silicon-tested and proposed fixes for crystal oscillator failure happened once in a while in an existing product in the market. Debugged and proposed yield improvement for the existing product.
• Designed PECL I/O Buffer, Level Detector, and Carrier Detector for 50-200MHz SERDES transceiver
• Designed Bandgap Reference, Bias current circuits in 3.0V and 1.8V supplies
• Designed CMOS Rail to Rail OpAmp & 50MHz Comparator with Offset Cancellation
• Debugged, fixed and simulated 6-bit Pipeline ADC
• Laid-out Bandgap and other circuits, ran DRC and LVS
• Characterized analog blocks, such as reference voltages and currents, detector, crystal oscillator, and some functional logics in the lab