Staff Analog & Mixed Signal IC Engineer Resume San Jose, CA - Hire IT People

SUMMARY:

An accomplished Analog & Mixed Signal design with startup and large company experience.
Designs from specification to introduction in volume production.
Team work oriented in multicultural multi - site environment.

TECHNICAL SKILLS

PROFESSIONAL EXPERIENCE

Confidential, San Jose, CA.

Staff Analog & Mixed Signal IC Engineer

Responsibilities:

High speed rail to rail common mode voltage differential receiver for DDRs, LVDS, SLVS utilizing teh UMC 40nm CMOS process IO devices.
High speed driver for LVDS, SLVS utilizing teh UMC 40nm CMOS process IO devices.
High Speed GPIO with VCCIO=1.2V~3.3V utilizing IO devices of UMC 40nm CMOS process.
ESD circuit and power clamp for IO and SERDES in UMC 40nm CMOS process.

Confidential, Mountain View, CA

Staff Analog & Mixed-Signal IC Engineer

Responsibilities:

Designed MIPI AFE HS mode RX circuits and LP mode Rx circuits using TSMC 40nm CMOS process
Ring VCO with operational frequency of 0.5GHz ~1GHz utilizing teh Jazz 0.18m CMOS process.
Bandgap bias circuit and voltage regulator etc. analog blocks utilizing Jazz 0.18m CMOS process.

Confidential, Sunnyvale, CA.

Member of Technical Staff

Responsibilities:

Voltage Controlled Oscillator (VCO) with operational frequency of 6336MHz for UWB applications utilizing teh TSMC 0.18m RFCMOS process.
UWB CLOCK Generation circuits to generate frequencies of 3432MHz, 3960MHz, and 4488MHz, circuits include PLL, Dividers, Single Side Band Mixers, MUX, and LO Buffers. These circuits were designed utilizing teh TSMC 0.18m RFCMOS technology.
UWB CLOCK Generation circuits such as PLLs, Dividers, Single Side Band Mixers, MUX, and LO Buffers. These circuits were designed to generate frequencies of 6600MHz, 7128MHz, 7656MHz, 8184MHz, 8712MHz, 9240MHz utilizing teh TSMC 0.13m RFCMOS technology.
300MHz Variable Gain Amplifier (VGA) with gain steps of 6dB and 1dB for UWB applications utilizing teh TSMC 0.18m RFCMOS process.
Phase Selection circuit which shifts LO signal phase by 0, 90, 180, 270 degrees.

Confidential, Los Gatos, CA

Senior RFIC Design Engineer

Responsibilities:

2GHz Low Noise Amplifier (LNA) and Sub-sampler (which downconverts a 2GHz signal into 125MHz) for PCS applications utilizing teh IBM BiCMOS5HPE technology.
Baseband linear-in-dB VGA for CDMA and AMPS applications utilizing teh IBM BiCMOS5HPE technology.

Confidential, Cerritos, CA

RFIC Design Engineer

Responsibilities:

800MHz IF PGA and IF Mixer block (which downconverts an 800MHz signal to baseband), Base Band PGA, analog and digital DC offset cancellation for IEEE802.11a WLAN applications utilizing teh TSMC 0.18m RFCMOS process.
2.4GHz RF Front-End section (LNA, Image Rejection Mixer, Polyphase, IF Buffer) for ISM application utilizing teh IBM BiCMOS5S technology.
900MHz RF Front-End (LNA, Image Rejection Mixer, Polyphase, IF Buffer) for ISM applications utilizing teh IBM BiCMOS4S technology.
280MHz and 900MHz RF Mixer for Pager applications utilizing teh TSMC 0.35m CMOS process.

Confidential, Irvine, CA

Research Assistant

Responsibilities:

Research in teh field of Analog IC design, and semiconductor devices.
Design and physical layout of continuous time Gm-C filter with teh HP 0.35m CMOS process.