SUMMARY

• An analytical and results - oriented engineer wif a proven track record of accomplishments in Design Verification and Engineering Design Automation.
• Over 12 years of wide experience in VLSI developing IP/SoC verification environment and ASIC, FPGA design. Have taken advantage of strong design/verification skills to continually develop hardware, verification components and test bench environment in my engineering work for productivity and quality enhancement. Strong team player wif a solid commitment to excellence contributes to the long-term success of a company.

TECHNICAL SKILLS

HDL Languages: Verilog, System Verilog, VHDL

Simulation tools: VCS, Modelsim, IRUN Cadence IES

Debug tools: IES Incisive Debug Analyzer

FPGAtools: Xilinx ISE, Alter Quartus II

HVL: Specman- e, System Verilog, C++

Verification Methodology: UVM using SV & eRM using Specman-e

Coverage: Modelsim, ICCR/IMC cadence.

Assertion: Atrenta BugScope.

Operating Systems: Windows / UNIX / Linux / Solaris

Programming Languages: HDL, C, C++

Scripting Language: Perl, Shell

Linting Tool: SpyGlass, HAL

Revision Control System: Cleartool and BDM.

Ethernet protocols: WLAN PHY/MAC Layer, 802.11a/b/g.

Bus Protocols: USB, ATA, OCP, AMBA ATB, AXI3, APB, AHB.

Debug & Trace: Debug SubSystem and TI DebugSS

Processor: ARM Cortex, TI-OMAP Processors.

PROFESSIONAL EXPERIENCE

Confidential, Texas

Engineering Design Automation

Responsibilities:

• Created verification and test plan.
• Created the test bench suite and developed verification environment using UVM methodology.
• Developed UVM components like drivers, monitors, scoreboards and checkers.
• Created the common test sequences and scenarios.
• Writing assertions and checkers at Module and SoC DV environment.
• Identified and created tests to perform design verification of DebugSS IP’s.
• Simulation, debugging and reporting bugs to design team.
• Identifying & creating the functional cover groups.
• Identified and created the tests for functional verification.
• Running the regression and generating coverage reports.
• Responsible for handling the DV activities and leading the verification team.

Confidential, Texas

Responsibilities:

• Created the DV and Test plan for Debug Sub system of MCU, OMAP and DSP devices.
• Developed DV environment using Specman-e eRM methodology and setting up the DV flow.
• Integration of the JTAG, APB & ATB eVC’s and Bus protocol eVC’s like OCP, AXI3 and STPv2.
• Verifying the integration of core sight components CTI, TPIU, Funnel and ATB Sources at SoC level.
• Involvement wif team members on the debugging, sequence creation and eVC porting.
• Worked on setting up the GLS (No timing) environment and running the regression on the same.
• Creating TBR and trigger/flush tests as per plan.
• Functional tests are created and verified integrated modules.
• Responsible for handling the DV activities like review, coverage analysis and leading the verification team.
• Was the verification team’s primary interface to the design team to provide focus for all DV issues and enhancement requests.

Confidential

Responsibilities:

• Created Verification Plan & Test matrix for PATA, VLYNQ and UART from SOC and IP design specifications.
• Involved in development and support for chip TB environment.
• Performed design verification of many different IP’s using VMM in chip context (was involved from start to finish on 2 different chips). Familiar wif digital test-benches, C and ASM test development.
• Identified the test cases, debugged and verified at RTL and gate level wif SDF annotation.
• Test Execution, Debug, Identification of Critical Integration Bugs and Reporting the Same.
• Code Coverage Reports and Analysis
• TDL Generation and Simulation at RTL/Gate.
• In parallel performed the flow customization and automation work for the DV team, including setup of the overall design verification environment for each chip.

Confidential

Responsibilities:

• Understanding of the PHY Specification.
• Verification Plan Creation.
• Test Bench Module Coding in Verilog.
• Module and System Level Verification.
• Test Execution and Debug, Bug Reporting.
• Code Coverage Reports and Analysis.
• Develop and Support Complete Integrated 802.11g - PHY Verification Environment Flow.

Confidential

Responsibilities:

• Understanding of the PHY Specification.
• Validation Plan Creation for Synthesizable Test Bench Controller.
• Synthesizable Test Bench Micro- Architecture Document Creation.
• Test Bench Module Coding in Verilog.
• Integration, FPGA Top Level Creation.
• Three Different FPGA Top Levels Created to Suite the Customer Requirement of Three Different Pin Bond Options.
• Synthesis, Timing Analysis and Fixing of Timing Violations.
• Enhancement of Test Bench Controller Code to Meet the Area Requirement of FPGA.
• Verification, Netlist Simulation of the Test Bench Controller.
• USB Compliance Tests Creation for Phy Validation.
• Execution, Debug of Compliance Tests on the Reference Phy as well as the DUT.
• System design: designed satellite payload data collector and video data formatter.
• FPGA Synthesis, Timing Violation Analysis.
• Minimal functional verification at RTL and Gate Level.
• Prototype Testing on the Board.